1 /* 2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #ifndef _ASM_ARC_ARCREGS_H 10 #define _ASM_ARC_ARCREGS_H 11 12 /* Build Configuration Registers */ 13 #define ARC_REG_DCCMBASE_BCR 0x61 /* DCCM Base Addr */ 14 #define ARC_REG_CRC_BCR 0x62 15 #define ARC_REG_VECBASE_BCR 0x68 16 #define ARC_REG_PERIBASE_BCR 0x69 17 #define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */ 18 #define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */ 19 #define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */ 20 #define ARC_REG_SLC_BCR 0xce 21 #define ARC_REG_DCCM_BCR 0x74 /* DCCM Present + SZ */ 22 #define ARC_REG_TIMERS_BCR 0x75 23 #define ARC_REG_AP_BCR 0x76 24 #define ARC_REG_ICCM_BCR 0x78 25 #define ARC_REG_XY_MEM_BCR 0x79 26 #define ARC_REG_MAC_BCR 0x7a 27 #define ARC_REG_MUL_BCR 0x7b 28 #define ARC_REG_SWAP_BCR 0x7c 29 #define ARC_REG_NORM_BCR 0x7d 30 #define ARC_REG_MIXMAX_BCR 0x7e 31 #define ARC_REG_BARREL_BCR 0x7f 32 #define ARC_REG_D_UNCACH_BCR 0x6A 33 #define ARC_REG_BPU_BCR 0xc0 34 #define ARC_REG_ISA_CFG_BCR 0xc1 35 #define ARC_REG_RTT_BCR 0xF2 36 #define ARC_REG_IRQ_BCR 0xF3 37 #define ARC_REG_SMART_BCR 0xFF 38 39 /* status32 Bits Positions */ 40 #define STATUS_AE_BIT 5 /* Exception active */ 41 #define STATUS_DE_BIT 6 /* PC is in delay slot */ 42 #define STATUS_U_BIT 7 /* User/Kernel mode */ 43 #define STATUS_L_BIT 12 /* Loop inhibit */ 44 45 /* These masks correspond to the status word(STATUS_32) bits */ 46 #define STATUS_AE_MASK (1<<STATUS_AE_BIT) 47 #define STATUS_DE_MASK (1<<STATUS_DE_BIT) 48 #define STATUS_U_MASK (1<<STATUS_U_BIT) 49 #define STATUS_L_MASK (1<<STATUS_L_BIT) 50 51 /* 52 * ECR: Exception Cause Reg bits-n-pieces 53 * [23:16] = Exception Vector 54 * [15: 8] = Exception Cause Code 55 * [ 7: 0] = Exception Parameters (for certain types only) 56 */ 57 #ifdef CONFIG_ISA_ARCOMPACT 58 #define ECR_V_MEM_ERR 0x01 59 #define ECR_V_INSN_ERR 0x02 60 #define ECR_V_MACH_CHK 0x20 61 #define ECR_V_ITLB_MISS 0x21 62 #define ECR_V_DTLB_MISS 0x22 63 #define ECR_V_PROTV 0x23 64 #define ECR_V_TRAP 0x25 65 #else 66 #define ECR_V_MEM_ERR 0x01 67 #define ECR_V_INSN_ERR 0x02 68 #define ECR_V_MACH_CHK 0x03 69 #define ECR_V_ITLB_MISS 0x04 70 #define ECR_V_DTLB_MISS 0x05 71 #define ECR_V_PROTV 0x06 72 #define ECR_V_TRAP 0x09 73 #endif 74 75 /* DTLB Miss and Protection Violation Cause Codes */ 76 77 #define ECR_C_PROTV_INST_FETCH 0x00 78 #define ECR_C_PROTV_LOAD 0x01 79 #define ECR_C_PROTV_STORE 0x02 80 #define ECR_C_PROTV_XCHG 0x03 81 #define ECR_C_PROTV_MISALIG_DATA 0x04 82 83 #define ECR_C_BIT_PROTV_MISALIG_DATA 10 84 85 /* Machine Check Cause Code Values */ 86 #define ECR_C_MCHK_DUP_TLB 0x01 87 88 /* DTLB Miss Exception Cause Code Values */ 89 #define ECR_C_BIT_DTLB_LD_MISS 8 90 #define ECR_C_BIT_DTLB_ST_MISS 9 91 92 /* Auxiliary registers */ 93 #define AUX_IDENTITY 4 94 #define AUX_INTR_VEC_BASE 0x25 95 #define AUX_NON_VOL 0x5e 96 97 /* 98 * Floating Pt Registers 99 * Status regs are read-only (build-time) so need not be saved/restored 100 */ 101 #define ARC_AUX_FP_STAT 0x300 102 #define ARC_AUX_DPFP_1L 0x301 103 #define ARC_AUX_DPFP_1H 0x302 104 #define ARC_AUX_DPFP_2L 0x303 105 #define ARC_AUX_DPFP_2H 0x304 106 #define ARC_AUX_DPFP_STAT 0x305 107 108 #ifndef __ASSEMBLY__ 109 110 /* 111 ****************************************************************** 112 * Inline ASM macros to read/write AUX Regs 113 * Essentially invocation of lr/sr insns from "C" 114 */ 115 116 #if 1 117 118 #define read_aux_reg(reg) __builtin_arc_lr(reg) 119 120 /* gcc builtin sr needs reg param to be long immediate */ 121 #define write_aux_reg(reg_immed, val) \ 122 __builtin_arc_sr((unsigned int)val, reg_immed) 123 124 #else 125 126 #define read_aux_reg(reg) \ 127 ({ \ 128 unsigned int __ret; \ 129 __asm__ __volatile__( \ 130 " lr %0, [%1]" \ 131 : "=r"(__ret) \ 132 : "i"(reg)); \ 133 __ret; \ 134 }) 135 136 /* 137 * Aux Reg address is specified as long immediate by caller 138 * e.g. 139 * write_aux_reg(0x69, some_val); 140 * This generates tightest code. 141 */ 142 #define write_aux_reg(reg_imm, val) \ 143 ({ \ 144 __asm__ __volatile__( \ 145 " sr %0, [%1] \n" \ 146 : \ 147 : "ir"(val), "i"(reg_imm)); \ 148 }) 149 150 /* 151 * Aux Reg address is specified in a variable 152 * * e.g. 153 * reg_num = 0x69 154 * write_aux_reg2(reg_num, some_val); 155 * This has to generate glue code to load the reg num from 156 * memory to a reg hence not recommended. 157 */ 158 #define write_aux_reg2(reg_in_var, val) \ 159 ({ \ 160 unsigned int tmp; \ 161 \ 162 __asm__ __volatile__( \ 163 " ld %0, [%2] \n\t" \ 164 " sr %1, [%0] \n\t" \ 165 : "=&r"(tmp) \ 166 : "r"(val), "memory"(®_in_var)); \ 167 }) 168 169 #endif 170 171 #define READ_BCR(reg, into) \ 172 { \ 173 unsigned int tmp; \ 174 tmp = read_aux_reg(reg); \ 175 if (sizeof(tmp) == sizeof(into)) { \ 176 into = *((typeof(into) *)&tmp); \ 177 } else { \ 178 extern void bogus_undefined(void); \ 179 bogus_undefined(); \ 180 } \ 181 } 182 183 #define WRITE_AUX(reg, into) \ 184 { \ 185 unsigned int tmp; \ 186 if (sizeof(tmp) == sizeof(into)) { \ 187 tmp = (*(unsigned int *)&(into)); \ 188 write_aux_reg(reg, tmp); \ 189 } else { \ 190 extern void bogus_undefined(void); \ 191 bogus_undefined(); \ 192 } \ 193 } 194 195 /* Helpers */ 196 #define TO_KB(bytes) ((bytes) >> 10) 197 #define TO_MB(bytes) (TO_KB(bytes) >> 10) 198 #define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10)) 199 #define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10) 200 201 202 /* 203 *************************************************************** 204 * Build Configuration Registers, with encoded hardware config 205 */ 206 struct bcr_identity { 207 #ifdef CONFIG_CPU_BIG_ENDIAN 208 unsigned int chip_id:16, cpu_id:8, family:8; 209 #else 210 unsigned int family:8, cpu_id:8, chip_id:16; 211 #endif 212 }; 213 214 struct bcr_isa { 215 #ifdef CONFIG_CPU_BIG_ENDIAN 216 unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1, 217 pad1:11, atomic1:1, ver:8; 218 #else 219 unsigned int ver:8, atomic1:1, pad1:11, be:1, atomic:1, unalign:1, 220 ldd:1, pad2:4, div_rem:4; 221 #endif 222 }; 223 224 struct bcr_mpy { 225 #ifdef CONFIG_CPU_BIG_ENDIAN 226 unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8; 227 #else 228 unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8; 229 #endif 230 }; 231 232 struct bcr_extn_xymem { 233 #ifdef CONFIG_CPU_BIG_ENDIAN 234 unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8; 235 #else 236 unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2; 237 #endif 238 }; 239 240 struct bcr_perip { 241 #ifdef CONFIG_CPU_BIG_ENDIAN 242 unsigned int start:8, pad2:8, sz:8, ver:8; 243 #else 244 unsigned int ver:8, sz:8, pad2:8, start:8; 245 #endif 246 }; 247 248 struct bcr_iccm { 249 #ifdef CONFIG_CPU_BIG_ENDIAN 250 unsigned int base:16, pad:5, sz:3, ver:8; 251 #else 252 unsigned int ver:8, sz:3, pad:5, base:16; 253 #endif 254 }; 255 256 /* DCCM Base Address Register: ARC_REG_DCCMBASE_BCR */ 257 struct bcr_dccm_base { 258 #ifdef CONFIG_CPU_BIG_ENDIAN 259 unsigned int addr:24, ver:8; 260 #else 261 unsigned int ver:8, addr:24; 262 #endif 263 }; 264 265 /* DCCM RAM Configuration Register: ARC_REG_DCCM_BCR */ 266 struct bcr_dccm { 267 #ifdef CONFIG_CPU_BIG_ENDIAN 268 unsigned int res:21, sz:3, ver:8; 269 #else 270 unsigned int ver:8, sz:3, res:21; 271 #endif 272 }; 273 274 /* ARCompact: Both SP and DP FPU BCRs have same format */ 275 struct bcr_fp_arcompact { 276 #ifdef CONFIG_CPU_BIG_ENDIAN 277 unsigned int fast:1, ver:8; 278 #else 279 unsigned int ver:8, fast:1; 280 #endif 281 }; 282 283 struct bcr_fp_arcv2 { 284 #ifdef CONFIG_CPU_BIG_ENDIAN 285 unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8; 286 #else 287 unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15; 288 #endif 289 }; 290 291 struct bcr_timer { 292 #ifdef CONFIG_CPU_BIG_ENDIAN 293 unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8; 294 #else 295 unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15; 296 #endif 297 }; 298 299 struct bcr_bpu_arcompact { 300 #ifdef CONFIG_CPU_BIG_ENDIAN 301 unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8; 302 #else 303 unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19; 304 #endif 305 }; 306 307 struct bcr_bpu_arcv2 { 308 #ifdef CONFIG_CPU_BIG_ENDIAN 309 unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8; 310 #else 311 unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6; 312 #endif 313 }; 314 315 struct bcr_generic { 316 #ifdef CONFIG_CPU_BIG_ENDIAN 317 unsigned int pad:24, ver:8; 318 #else 319 unsigned int ver:8, pad:24; 320 #endif 321 }; 322 323 /* 324 ******************************************************************* 325 * Generic structures to hold build configuration used at runtime 326 */ 327 328 struct cpuinfo_arc_mmu { 329 unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, u_dtlb:6, u_itlb:6; 330 unsigned int num_tlb:16, sets:12, ways:4; 331 }; 332 333 struct cpuinfo_arc_cache { 334 unsigned int sz_k:14, line_len:8, assoc:4, ver:4, alias:1, vipt:1; 335 }; 336 337 struct cpuinfo_arc_bpu { 338 unsigned int ver, full, num_cache, num_pred; 339 }; 340 341 struct cpuinfo_arc_ccm { 342 unsigned int base_addr, sz; 343 }; 344 345 struct cpuinfo_arc { 346 struct cpuinfo_arc_cache icache, dcache, slc; 347 struct cpuinfo_arc_mmu mmu; 348 struct cpuinfo_arc_bpu bpu; 349 struct bcr_identity core; 350 struct bcr_isa isa; 351 struct bcr_timer timers; 352 unsigned int vec_base; 353 struct cpuinfo_arc_ccm iccm, dccm; 354 struct { 355 unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, pad1:3, 356 fpu_sp:1, fpu_dp:1, pad2:6, 357 debug:1, ap:1, smart:1, rtt:1, pad3:4, 358 pad4:8; 359 } extn; 360 struct bcr_mpy extn_mpy; 361 struct bcr_extn_xymem extn_xymem; 362 }; 363 364 extern struct cpuinfo_arc cpuinfo_arc700[]; 365 366 static inline int is_isa_arcv2(void) 367 { 368 return IS_ENABLED(CONFIG_ISA_ARCV2); 369 } 370 371 static inline int is_isa_arcompact(void) 372 { 373 return IS_ENABLED(CONFIG_ISA_ARCOMPACT); 374 } 375 376 #if defined(CONFIG_ISA_ARCOMPACT) && !defined(_CPU_DEFAULT_A7) 377 #error "Toolchain not configured for ARCompact builds" 378 #elif defined(CONFIG_ISA_ARCV2) && !defined(_CPU_DEFAULT_HS) 379 #error "Toolchain not configured for ARCv2 builds" 380 #endif 381 382 #endif /* __ASEMBLY__ */ 383 384 #endif /* _ASM_ARC_ARCREGS_H */ 385