1 /* 2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #ifndef _ASM_ARC_ARCREGS_H 10 #define _ASM_ARC_ARCREGS_H 11 12 /* Build Configuration Registers */ 13 #define ARC_REG_DCCMBASE_BCR 0x61 /* DCCM Base Addr */ 14 #define ARC_REG_CRC_BCR 0x62 15 #define ARC_REG_VECBASE_BCR 0x68 16 #define ARC_REG_PERIBASE_BCR 0x69 17 #define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */ 18 #define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */ 19 #define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */ 20 #define ARC_REG_SLC_BCR 0xce 21 #define ARC_REG_DCCM_BCR 0x74 /* DCCM Present + SZ */ 22 #define ARC_REG_TIMERS_BCR 0x75 23 #define ARC_REG_AP_BCR 0x76 24 #define ARC_REG_ICCM_BCR 0x78 25 #define ARC_REG_XY_MEM_BCR 0x79 26 #define ARC_REG_MAC_BCR 0x7a 27 #define ARC_REG_MUL_BCR 0x7b 28 #define ARC_REG_SWAP_BCR 0x7c 29 #define ARC_REG_NORM_BCR 0x7d 30 #define ARC_REG_MIXMAX_BCR 0x7e 31 #define ARC_REG_BARREL_BCR 0x7f 32 #define ARC_REG_D_UNCACH_BCR 0x6A 33 #define ARC_REG_BPU_BCR 0xc0 34 #define ARC_REG_ISA_CFG_BCR 0xc1 35 #define ARC_REG_RTT_BCR 0xF2 36 #define ARC_REG_IRQ_BCR 0xF3 37 #define ARC_REG_SMART_BCR 0xFF 38 #define ARC_REG_CLUSTER_BCR 0xcf 39 40 /* status32 Bits Positions */ 41 #define STATUS_AE_BIT 5 /* Exception active */ 42 #define STATUS_DE_BIT 6 /* PC is in delay slot */ 43 #define STATUS_U_BIT 7 /* User/Kernel mode */ 44 #define STATUS_L_BIT 12 /* Loop inhibit */ 45 46 /* These masks correspond to the status word(STATUS_32) bits */ 47 #define STATUS_AE_MASK (1<<STATUS_AE_BIT) 48 #define STATUS_DE_MASK (1<<STATUS_DE_BIT) 49 #define STATUS_U_MASK (1<<STATUS_U_BIT) 50 #define STATUS_L_MASK (1<<STATUS_L_BIT) 51 52 /* 53 * ECR: Exception Cause Reg bits-n-pieces 54 * [23:16] = Exception Vector 55 * [15: 8] = Exception Cause Code 56 * [ 7: 0] = Exception Parameters (for certain types only) 57 */ 58 #ifdef CONFIG_ISA_ARCOMPACT 59 #define ECR_V_MEM_ERR 0x01 60 #define ECR_V_INSN_ERR 0x02 61 #define ECR_V_MACH_CHK 0x20 62 #define ECR_V_ITLB_MISS 0x21 63 #define ECR_V_DTLB_MISS 0x22 64 #define ECR_V_PROTV 0x23 65 #define ECR_V_TRAP 0x25 66 #else 67 #define ECR_V_MEM_ERR 0x01 68 #define ECR_V_INSN_ERR 0x02 69 #define ECR_V_MACH_CHK 0x03 70 #define ECR_V_ITLB_MISS 0x04 71 #define ECR_V_DTLB_MISS 0x05 72 #define ECR_V_PROTV 0x06 73 #define ECR_V_TRAP 0x09 74 #endif 75 76 /* DTLB Miss and Protection Violation Cause Codes */ 77 78 #define ECR_C_PROTV_INST_FETCH 0x00 79 #define ECR_C_PROTV_LOAD 0x01 80 #define ECR_C_PROTV_STORE 0x02 81 #define ECR_C_PROTV_XCHG 0x03 82 #define ECR_C_PROTV_MISALIG_DATA 0x04 83 84 #define ECR_C_BIT_PROTV_MISALIG_DATA 10 85 86 /* Machine Check Cause Code Values */ 87 #define ECR_C_MCHK_DUP_TLB 0x01 88 89 /* DTLB Miss Exception Cause Code Values */ 90 #define ECR_C_BIT_DTLB_LD_MISS 8 91 #define ECR_C_BIT_DTLB_ST_MISS 9 92 93 /* Auxiliary registers */ 94 #define AUX_IDENTITY 4 95 #define AUX_INTR_VEC_BASE 0x25 96 #define AUX_NON_VOL 0x5e 97 98 /* 99 * Floating Pt Registers 100 * Status regs are read-only (build-time) so need not be saved/restored 101 */ 102 #define ARC_AUX_FP_STAT 0x300 103 #define ARC_AUX_DPFP_1L 0x301 104 #define ARC_AUX_DPFP_1H 0x302 105 #define ARC_AUX_DPFP_2L 0x303 106 #define ARC_AUX_DPFP_2H 0x304 107 #define ARC_AUX_DPFP_STAT 0x305 108 109 #ifndef __ASSEMBLY__ 110 111 /* 112 ****************************************************************** 113 * Inline ASM macros to read/write AUX Regs 114 * Essentially invocation of lr/sr insns from "C" 115 */ 116 117 #if 1 118 119 #define read_aux_reg(reg) __builtin_arc_lr(reg) 120 121 /* gcc builtin sr needs reg param to be long immediate */ 122 #define write_aux_reg(reg_immed, val) \ 123 __builtin_arc_sr((unsigned int)(val), reg_immed) 124 125 #else 126 127 #define read_aux_reg(reg) \ 128 ({ \ 129 unsigned int __ret; \ 130 __asm__ __volatile__( \ 131 " lr %0, [%1]" \ 132 : "=r"(__ret) \ 133 : "i"(reg)); \ 134 __ret; \ 135 }) 136 137 /* 138 * Aux Reg address is specified as long immediate by caller 139 * e.g. 140 * write_aux_reg(0x69, some_val); 141 * This generates tightest code. 142 */ 143 #define write_aux_reg(reg_imm, val) \ 144 ({ \ 145 __asm__ __volatile__( \ 146 " sr %0, [%1] \n" \ 147 : \ 148 : "ir"(val), "i"(reg_imm)); \ 149 }) 150 151 /* 152 * Aux Reg address is specified in a variable 153 * * e.g. 154 * reg_num = 0x69 155 * write_aux_reg2(reg_num, some_val); 156 * This has to generate glue code to load the reg num from 157 * memory to a reg hence not recommended. 158 */ 159 #define write_aux_reg2(reg_in_var, val) \ 160 ({ \ 161 unsigned int tmp; \ 162 \ 163 __asm__ __volatile__( \ 164 " ld %0, [%2] \n\t" \ 165 " sr %1, [%0] \n\t" \ 166 : "=&r"(tmp) \ 167 : "r"(val), "memory"(®_in_var)); \ 168 }) 169 170 #endif 171 172 #define READ_BCR(reg, into) \ 173 { \ 174 unsigned int tmp; \ 175 tmp = read_aux_reg(reg); \ 176 if (sizeof(tmp) == sizeof(into)) { \ 177 into = *((typeof(into) *)&tmp); \ 178 } else { \ 179 extern void bogus_undefined(void); \ 180 bogus_undefined(); \ 181 } \ 182 } 183 184 #define WRITE_AUX(reg, into) \ 185 { \ 186 unsigned int tmp; \ 187 if (sizeof(tmp) == sizeof(into)) { \ 188 tmp = (*(unsigned int *)&(into)); \ 189 write_aux_reg(reg, tmp); \ 190 } else { \ 191 extern void bogus_undefined(void); \ 192 bogus_undefined(); \ 193 } \ 194 } 195 196 /* Helpers */ 197 #define TO_KB(bytes) ((bytes) >> 10) 198 #define TO_MB(bytes) (TO_KB(bytes) >> 10) 199 #define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10)) 200 #define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10) 201 202 203 /* 204 *************************************************************** 205 * Build Configuration Registers, with encoded hardware config 206 */ 207 struct bcr_identity { 208 #ifdef CONFIG_CPU_BIG_ENDIAN 209 unsigned int chip_id:16, cpu_id:8, family:8; 210 #else 211 unsigned int family:8, cpu_id:8, chip_id:16; 212 #endif 213 }; 214 215 struct bcr_isa { 216 #ifdef CONFIG_CPU_BIG_ENDIAN 217 unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1, 218 pad1:11, atomic1:1, ver:8; 219 #else 220 unsigned int ver:8, atomic1:1, pad1:11, be:1, atomic:1, unalign:1, 221 ldd:1, pad2:4, div_rem:4; 222 #endif 223 }; 224 225 struct bcr_mpy { 226 #ifdef CONFIG_CPU_BIG_ENDIAN 227 unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8; 228 #else 229 unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8; 230 #endif 231 }; 232 233 struct bcr_extn_xymem { 234 #ifdef CONFIG_CPU_BIG_ENDIAN 235 unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8; 236 #else 237 unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2; 238 #endif 239 }; 240 241 struct bcr_perip { 242 #ifdef CONFIG_CPU_BIG_ENDIAN 243 unsigned int start:8, pad2:8, sz:8, ver:8; 244 #else 245 unsigned int ver:8, sz:8, pad2:8, start:8; 246 #endif 247 }; 248 249 struct bcr_iccm { 250 #ifdef CONFIG_CPU_BIG_ENDIAN 251 unsigned int base:16, pad:5, sz:3, ver:8; 252 #else 253 unsigned int ver:8, sz:3, pad:5, base:16; 254 #endif 255 }; 256 257 /* DCCM Base Address Register: ARC_REG_DCCMBASE_BCR */ 258 struct bcr_dccm_base { 259 #ifdef CONFIG_CPU_BIG_ENDIAN 260 unsigned int addr:24, ver:8; 261 #else 262 unsigned int ver:8, addr:24; 263 #endif 264 }; 265 266 /* DCCM RAM Configuration Register: ARC_REG_DCCM_BCR */ 267 struct bcr_dccm { 268 #ifdef CONFIG_CPU_BIG_ENDIAN 269 unsigned int res:21, sz:3, ver:8; 270 #else 271 unsigned int ver:8, sz:3, res:21; 272 #endif 273 }; 274 275 /* ARCompact: Both SP and DP FPU BCRs have same format */ 276 struct bcr_fp_arcompact { 277 #ifdef CONFIG_CPU_BIG_ENDIAN 278 unsigned int fast:1, ver:8; 279 #else 280 unsigned int ver:8, fast:1; 281 #endif 282 }; 283 284 struct bcr_fp_arcv2 { 285 #ifdef CONFIG_CPU_BIG_ENDIAN 286 unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8; 287 #else 288 unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15; 289 #endif 290 }; 291 292 struct bcr_timer { 293 #ifdef CONFIG_CPU_BIG_ENDIAN 294 unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8; 295 #else 296 unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15; 297 #endif 298 }; 299 300 struct bcr_bpu_arcompact { 301 #ifdef CONFIG_CPU_BIG_ENDIAN 302 unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8; 303 #else 304 unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19; 305 #endif 306 }; 307 308 struct bcr_bpu_arcv2 { 309 #ifdef CONFIG_CPU_BIG_ENDIAN 310 unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8; 311 #else 312 unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6; 313 #endif 314 }; 315 316 struct bcr_generic { 317 #ifdef CONFIG_CPU_BIG_ENDIAN 318 unsigned int pad:24, ver:8; 319 #else 320 unsigned int ver:8, pad:24; 321 #endif 322 }; 323 324 /* 325 ******************************************************************* 326 * Generic structures to hold build configuration used at runtime 327 */ 328 329 struct cpuinfo_arc_mmu { 330 unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:10, sasid:1, pae:1; 331 unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8; 332 }; 333 334 struct cpuinfo_arc_cache { 335 unsigned int sz_k:14, line_len:8, assoc:4, ver:4, alias:1, vipt:1; 336 }; 337 338 struct cpuinfo_arc_bpu { 339 unsigned int ver, full, num_cache, num_pred; 340 }; 341 342 struct cpuinfo_arc_ccm { 343 unsigned int base_addr, sz; 344 }; 345 346 struct cpuinfo_arc { 347 struct cpuinfo_arc_cache icache, dcache, slc; 348 struct cpuinfo_arc_mmu mmu; 349 struct cpuinfo_arc_bpu bpu; 350 struct bcr_identity core; 351 struct bcr_isa isa; 352 struct bcr_timer timers; 353 unsigned int vec_base; 354 struct cpuinfo_arc_ccm iccm, dccm; 355 struct { 356 unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, pad1:3, 357 fpu_sp:1, fpu_dp:1, pad2:6, 358 debug:1, ap:1, smart:1, rtt:1, pad3:4, 359 pad4:8; 360 } extn; 361 struct bcr_mpy extn_mpy; 362 struct bcr_extn_xymem extn_xymem; 363 }; 364 365 extern struct cpuinfo_arc cpuinfo_arc700[]; 366 367 static inline int is_isa_arcv2(void) 368 { 369 return IS_ENABLED(CONFIG_ISA_ARCV2); 370 } 371 372 static inline int is_isa_arcompact(void) 373 { 374 return IS_ENABLED(CONFIG_ISA_ARCOMPACT); 375 } 376 377 #if defined(CONFIG_ISA_ARCOMPACT) && !defined(_CPU_DEFAULT_A7) 378 #error "Toolchain not configured for ARCompact builds" 379 #elif defined(CONFIG_ISA_ARCV2) && !defined(_CPU_DEFAULT_HS) 380 #error "Toolchain not configured for ARCv2 builds" 381 #endif 382 383 #endif /* __ASEMBLY__ */ 384 385 #endif /* _ASM_ARC_ARCREGS_H */ 386