1 /* 2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #ifndef _ASM_ARC_ARCREGS_H 10 #define _ASM_ARC_ARCREGS_H 11 12 /* Build Configuration Registers */ 13 #define ARC_REG_AUX_DCCM 0x18 /* DCCM Base Addr ARCv2 */ 14 #define ARC_REG_ERP_CTRL 0x3F /* ARCv2 Error protection control */ 15 #define ARC_REG_DCCM_BASE_BUILD 0x61 /* DCCM Base Addr ARCompact */ 16 #define ARC_REG_CRC_BCR 0x62 17 #define ARC_REG_VECBASE_BCR 0x68 18 #define ARC_REG_PERIBASE_BCR 0x69 19 #define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */ 20 #define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */ 21 #define ARC_REG_ERP_BUILD 0xc7 /* ARCv2 Error protection Build: ECC/Parity */ 22 #define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */ 23 #define ARC_REG_SLC_BCR 0xce 24 #define ARC_REG_DCCM_BUILD 0x74 /* DCCM size (common) */ 25 #define ARC_REG_AP_BCR 0x76 26 #define ARC_REG_ICCM_BUILD 0x78 /* ICCM size (common) */ 27 #define ARC_REG_XY_MEM_BCR 0x79 28 #define ARC_REG_MAC_BCR 0x7a 29 #define ARC_REG_MUL_BCR 0x7b 30 #define ARC_REG_SWAP_BCR 0x7c 31 #define ARC_REG_NORM_BCR 0x7d 32 #define ARC_REG_MIXMAX_BCR 0x7e 33 #define ARC_REG_BARREL_BCR 0x7f 34 #define ARC_REG_D_UNCACH_BCR 0x6A 35 #define ARC_REG_BPU_BCR 0xc0 36 #define ARC_REG_ISA_CFG_BCR 0xc1 37 #define ARC_REG_LPB_BUILD 0xE9 /* ARCv2 Loop Buffer Build */ 38 #define ARC_REG_RTT_BCR 0xF2 39 #define ARC_REG_IRQ_BCR 0xF3 40 #define ARC_REG_MICRO_ARCH_BCR 0xF9 /* ARCv2 Product revision */ 41 #define ARC_REG_SMART_BCR 0xFF 42 #define ARC_REG_CLUSTER_BCR 0xcf 43 #define ARC_REG_AUX_ICCM 0x208 /* ICCM Base Addr (ARCv2) */ 44 #define ARC_REG_LPB_CTRL 0x488 /* ARCv2 Loop Buffer control */ 45 46 /* Common for ARCompact and ARCv2 status register */ 47 #define ARC_REG_STATUS32 0x0A 48 49 /* status32 Bits Positions */ 50 #define STATUS_AE_BIT 5 /* Exception active */ 51 #define STATUS_DE_BIT 6 /* PC is in delay slot */ 52 #define STATUS_U_BIT 7 /* User/Kernel mode */ 53 #define STATUS_Z_BIT 11 54 #define STATUS_L_BIT 12 /* Loop inhibit */ 55 56 /* These masks correspond to the status word(STATUS_32) bits */ 57 #define STATUS_AE_MASK (1<<STATUS_AE_BIT) 58 #define STATUS_DE_MASK (1<<STATUS_DE_BIT) 59 #define STATUS_U_MASK (1<<STATUS_U_BIT) 60 #define STATUS_Z_MASK (1<<STATUS_Z_BIT) 61 #define STATUS_L_MASK (1<<STATUS_L_BIT) 62 63 /* 64 * ECR: Exception Cause Reg bits-n-pieces 65 * [23:16] = Exception Vector 66 * [15: 8] = Exception Cause Code 67 * [ 7: 0] = Exception Parameters (for certain types only) 68 */ 69 #ifdef CONFIG_ISA_ARCOMPACT 70 #define ECR_V_MEM_ERR 0x01 71 #define ECR_V_INSN_ERR 0x02 72 #define ECR_V_MACH_CHK 0x20 73 #define ECR_V_ITLB_MISS 0x21 74 #define ECR_V_DTLB_MISS 0x22 75 #define ECR_V_PROTV 0x23 76 #define ECR_V_TRAP 0x25 77 #else 78 #define ECR_V_MEM_ERR 0x01 79 #define ECR_V_INSN_ERR 0x02 80 #define ECR_V_MACH_CHK 0x03 81 #define ECR_V_ITLB_MISS 0x04 82 #define ECR_V_DTLB_MISS 0x05 83 #define ECR_V_PROTV 0x06 84 #define ECR_V_TRAP 0x09 85 #endif 86 87 /* DTLB Miss and Protection Violation Cause Codes */ 88 89 #define ECR_C_PROTV_INST_FETCH 0x00 90 #define ECR_C_PROTV_LOAD 0x01 91 #define ECR_C_PROTV_STORE 0x02 92 #define ECR_C_PROTV_XCHG 0x03 93 #define ECR_C_PROTV_MISALIG_DATA 0x04 94 95 #define ECR_C_BIT_PROTV_MISALIG_DATA 10 96 97 /* Machine Check Cause Code Values */ 98 #define ECR_C_MCHK_DUP_TLB 0x01 99 100 /* DTLB Miss Exception Cause Code Values */ 101 #define ECR_C_BIT_DTLB_LD_MISS 8 102 #define ECR_C_BIT_DTLB_ST_MISS 9 103 104 /* Auxiliary registers */ 105 #define AUX_IDENTITY 4 106 #define AUX_EXEC_CTRL 8 107 #define AUX_INTR_VEC_BASE 0x25 108 #define AUX_VOL 0x5e 109 110 /* 111 * Floating Pt Registers 112 * Status regs are read-only (build-time) so need not be saved/restored 113 */ 114 #define ARC_AUX_FP_STAT 0x300 115 #define ARC_AUX_DPFP_1L 0x301 116 #define ARC_AUX_DPFP_1H 0x302 117 #define ARC_AUX_DPFP_2L 0x303 118 #define ARC_AUX_DPFP_2H 0x304 119 #define ARC_AUX_DPFP_STAT 0x305 120 121 #ifndef __ASSEMBLY__ 122 123 #include <soc/arc/aux.h> 124 125 /* Helpers */ 126 #define TO_KB(bytes) ((bytes) >> 10) 127 #define TO_MB(bytes) (TO_KB(bytes) >> 10) 128 #define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10)) 129 #define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10) 130 131 132 /* 133 *************************************************************** 134 * Build Configuration Registers, with encoded hardware config 135 */ 136 struct bcr_identity { 137 #ifdef CONFIG_CPU_BIG_ENDIAN 138 unsigned int chip_id:16, cpu_id:8, family:8; 139 #else 140 unsigned int family:8, cpu_id:8, chip_id:16; 141 #endif 142 }; 143 144 struct bcr_isa_arcv2 { 145 #ifdef CONFIG_CPU_BIG_ENDIAN 146 unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1, 147 pad1:12, ver:8; 148 #else 149 unsigned int ver:8, pad1:12, be:1, atomic:1, unalign:1, 150 ldd:1, pad2:4, div_rem:4; 151 #endif 152 }; 153 154 struct bcr_mpy { 155 #ifdef CONFIG_CPU_BIG_ENDIAN 156 unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8; 157 #else 158 unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8; 159 #endif 160 }; 161 162 struct bcr_extn_xymem { 163 #ifdef CONFIG_CPU_BIG_ENDIAN 164 unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8; 165 #else 166 unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2; 167 #endif 168 }; 169 170 struct bcr_iccm_arcompact { 171 #ifdef CONFIG_CPU_BIG_ENDIAN 172 unsigned int base:16, pad:5, sz:3, ver:8; 173 #else 174 unsigned int ver:8, sz:3, pad:5, base:16; 175 #endif 176 }; 177 178 struct bcr_iccm_arcv2 { 179 #ifdef CONFIG_CPU_BIG_ENDIAN 180 unsigned int pad:8, sz11:4, sz01:4, sz10:4, sz00:4, ver:8; 181 #else 182 unsigned int ver:8, sz00:4, sz10:4, sz01:4, sz11:4, pad:8; 183 #endif 184 }; 185 186 struct bcr_dccm_arcompact { 187 #ifdef CONFIG_CPU_BIG_ENDIAN 188 unsigned int res:21, sz:3, ver:8; 189 #else 190 unsigned int ver:8, sz:3, res:21; 191 #endif 192 }; 193 194 struct bcr_dccm_arcv2 { 195 #ifdef CONFIG_CPU_BIG_ENDIAN 196 unsigned int pad2:12, cyc:3, pad1:1, sz1:4, sz0:4, ver:8; 197 #else 198 unsigned int ver:8, sz0:4, sz1:4, pad1:1, cyc:3, pad2:12; 199 #endif 200 }; 201 202 /* ARCompact: Both SP and DP FPU BCRs have same format */ 203 struct bcr_fp_arcompact { 204 #ifdef CONFIG_CPU_BIG_ENDIAN 205 unsigned int fast:1, ver:8; 206 #else 207 unsigned int ver:8, fast:1; 208 #endif 209 }; 210 211 struct bcr_fp_arcv2 { 212 #ifdef CONFIG_CPU_BIG_ENDIAN 213 unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8; 214 #else 215 unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15; 216 #endif 217 }; 218 219 struct bcr_actionpoint { 220 #ifdef CONFIG_CPU_BIG_ENDIAN 221 unsigned int pad:21, min:1, num:2, ver:8; 222 #else 223 unsigned int ver:8, num:2, min:1, pad:21; 224 #endif 225 }; 226 227 #include <soc/arc/timers.h> 228 229 struct bcr_bpu_arcompact { 230 #ifdef CONFIG_CPU_BIG_ENDIAN 231 unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8; 232 #else 233 unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19; 234 #endif 235 }; 236 237 struct bcr_bpu_arcv2 { 238 #ifdef CONFIG_CPU_BIG_ENDIAN 239 unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8; 240 #else 241 unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6; 242 #endif 243 }; 244 245 /* Error Protection Build: ECC/Parity */ 246 struct bcr_erp { 247 #ifdef CONFIG_CPU_BIG_ENDIAN 248 unsigned int pad3:5, mmu:3, pad2:4, ic:3, dc:3, pad1:6, ver:8; 249 #else 250 unsigned int ver:8, pad1:6, dc:3, ic:3, pad2:4, mmu:3, pad3:5; 251 #endif 252 }; 253 254 /* Error Protection Control */ 255 struct ctl_erp { 256 #ifdef CONFIG_CPU_BIG_ENDIAN 257 unsigned int pad2:27, mpd:1, pad1:2, dpd:1, dpi:1; 258 #else 259 unsigned int dpi:1, dpd:1, pad1:2, mpd:1, pad2:27; 260 #endif 261 }; 262 263 struct bcr_lpb { 264 #ifdef CONFIG_CPU_BIG_ENDIAN 265 unsigned int pad:16, entries:8, ver:8; 266 #else 267 unsigned int ver:8, entries:8, pad:16; 268 #endif 269 }; 270 271 struct bcr_generic { 272 #ifdef CONFIG_CPU_BIG_ENDIAN 273 unsigned int info:24, ver:8; 274 #else 275 unsigned int ver:8, info:24; 276 #endif 277 }; 278 279 /* 280 ******************************************************************* 281 * Generic structures to hold build configuration used at runtime 282 */ 283 284 struct cpuinfo_arc_mmu { 285 unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:10, sasid:1, pae:1; 286 unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8; 287 }; 288 289 struct cpuinfo_arc_cache { 290 unsigned int sz_k:14, line_len:8, assoc:4, alias:1, vipt:1, pad:4; 291 }; 292 293 struct cpuinfo_arc_bpu { 294 unsigned int ver, full, num_cache, num_pred, ret_stk; 295 }; 296 297 struct cpuinfo_arc_ccm { 298 unsigned int base_addr, sz; 299 }; 300 301 struct cpuinfo_arc { 302 struct cpuinfo_arc_cache icache, dcache, slc; 303 struct cpuinfo_arc_mmu mmu; 304 struct cpuinfo_arc_bpu bpu; 305 struct bcr_identity core; 306 struct bcr_isa_arcv2 isa; 307 const char *details, *name; 308 unsigned int vec_base; 309 struct cpuinfo_arc_ccm iccm, dccm; 310 struct { 311 unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2, 312 fpu_sp:1, fpu_dp:1, dual:1, dual_enb:1, pad2:4, 313 ap_num:4, ap_full:1, smart:1, rtt:1, pad3:1, 314 timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4; 315 } extn; 316 struct bcr_mpy extn_mpy; 317 struct bcr_extn_xymem extn_xymem; 318 }; 319 320 extern struct cpuinfo_arc cpuinfo_arc700[]; 321 322 static inline int is_isa_arcv2(void) 323 { 324 return IS_ENABLED(CONFIG_ISA_ARCV2); 325 } 326 327 static inline int is_isa_arcompact(void) 328 { 329 return IS_ENABLED(CONFIG_ISA_ARCOMPACT); 330 } 331 332 #endif /* __ASEMBLY__ */ 333 334 #endif /* _ASM_ARC_ARCREGS_H */ 335