1 /* 2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #ifndef _ASM_ARC_ARCREGS_H 10 #define _ASM_ARC_ARCREGS_H 11 12 /* Build Configuration Registers */ 13 #define ARC_REG_AUX_DCCM 0x18 /* DCCM Base Addr ARCv2 */ 14 #define ARC_REG_DCCM_BASE_BUILD 0x61 /* DCCM Base Addr ARCompact */ 15 #define ARC_REG_CRC_BCR 0x62 16 #define ARC_REG_VECBASE_BCR 0x68 17 #define ARC_REG_PERIBASE_BCR 0x69 18 #define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */ 19 #define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */ 20 #define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */ 21 #define ARC_REG_SLC_BCR 0xce 22 #define ARC_REG_DCCM_BUILD 0x74 /* DCCM size (common) */ 23 #define ARC_REG_AP_BCR 0x76 24 #define ARC_REG_ICCM_BUILD 0x78 /* ICCM size (common) */ 25 #define ARC_REG_XY_MEM_BCR 0x79 26 #define ARC_REG_MAC_BCR 0x7a 27 #define ARC_REG_MUL_BCR 0x7b 28 #define ARC_REG_SWAP_BCR 0x7c 29 #define ARC_REG_NORM_BCR 0x7d 30 #define ARC_REG_MIXMAX_BCR 0x7e 31 #define ARC_REG_BARREL_BCR 0x7f 32 #define ARC_REG_D_UNCACH_BCR 0x6A 33 #define ARC_REG_BPU_BCR 0xc0 34 #define ARC_REG_ISA_CFG_BCR 0xc1 35 #define ARC_REG_RTT_BCR 0xF2 36 #define ARC_REG_IRQ_BCR 0xF3 37 #define ARC_REG_SMART_BCR 0xFF 38 #define ARC_REG_CLUSTER_BCR 0xcf 39 #define ARC_REG_AUX_ICCM 0x208 /* ICCM Base Addr (ARCv2) */ 40 41 /* Common for ARCompact and ARCv2 status register */ 42 #define ARC_REG_STATUS32 0x0A 43 44 /* status32 Bits Positions */ 45 #define STATUS_AE_BIT 5 /* Exception active */ 46 #define STATUS_DE_BIT 6 /* PC is in delay slot */ 47 #define STATUS_U_BIT 7 /* User/Kernel mode */ 48 #define STATUS_Z_BIT 11 49 #define STATUS_L_BIT 12 /* Loop inhibit */ 50 51 /* These masks correspond to the status word(STATUS_32) bits */ 52 #define STATUS_AE_MASK (1<<STATUS_AE_BIT) 53 #define STATUS_DE_MASK (1<<STATUS_DE_BIT) 54 #define STATUS_U_MASK (1<<STATUS_U_BIT) 55 #define STATUS_Z_MASK (1<<STATUS_Z_BIT) 56 #define STATUS_L_MASK (1<<STATUS_L_BIT) 57 58 /* 59 * ECR: Exception Cause Reg bits-n-pieces 60 * [23:16] = Exception Vector 61 * [15: 8] = Exception Cause Code 62 * [ 7: 0] = Exception Parameters (for certain types only) 63 */ 64 #ifdef CONFIG_ISA_ARCOMPACT 65 #define ECR_V_MEM_ERR 0x01 66 #define ECR_V_INSN_ERR 0x02 67 #define ECR_V_MACH_CHK 0x20 68 #define ECR_V_ITLB_MISS 0x21 69 #define ECR_V_DTLB_MISS 0x22 70 #define ECR_V_PROTV 0x23 71 #define ECR_V_TRAP 0x25 72 #else 73 #define ECR_V_MEM_ERR 0x01 74 #define ECR_V_INSN_ERR 0x02 75 #define ECR_V_MACH_CHK 0x03 76 #define ECR_V_ITLB_MISS 0x04 77 #define ECR_V_DTLB_MISS 0x05 78 #define ECR_V_PROTV 0x06 79 #define ECR_V_TRAP 0x09 80 #endif 81 82 /* DTLB Miss and Protection Violation Cause Codes */ 83 84 #define ECR_C_PROTV_INST_FETCH 0x00 85 #define ECR_C_PROTV_LOAD 0x01 86 #define ECR_C_PROTV_STORE 0x02 87 #define ECR_C_PROTV_XCHG 0x03 88 #define ECR_C_PROTV_MISALIG_DATA 0x04 89 90 #define ECR_C_BIT_PROTV_MISALIG_DATA 10 91 92 /* Machine Check Cause Code Values */ 93 #define ECR_C_MCHK_DUP_TLB 0x01 94 95 /* DTLB Miss Exception Cause Code Values */ 96 #define ECR_C_BIT_DTLB_LD_MISS 8 97 #define ECR_C_BIT_DTLB_ST_MISS 9 98 99 /* Auxiliary registers */ 100 #define AUX_IDENTITY 4 101 #define AUX_INTR_VEC_BASE 0x25 102 #define AUX_VOL 0x5e 103 104 /* 105 * Floating Pt Registers 106 * Status regs are read-only (build-time) so need not be saved/restored 107 */ 108 #define ARC_AUX_FP_STAT 0x300 109 #define ARC_AUX_DPFP_1L 0x301 110 #define ARC_AUX_DPFP_1H 0x302 111 #define ARC_AUX_DPFP_2L 0x303 112 #define ARC_AUX_DPFP_2H 0x304 113 #define ARC_AUX_DPFP_STAT 0x305 114 115 #ifndef __ASSEMBLY__ 116 117 #include <soc/arc/aux.h> 118 119 /* Helpers */ 120 #define TO_KB(bytes) ((bytes) >> 10) 121 #define TO_MB(bytes) (TO_KB(bytes) >> 10) 122 #define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10)) 123 #define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10) 124 125 126 /* 127 *************************************************************** 128 * Build Configuration Registers, with encoded hardware config 129 */ 130 struct bcr_identity { 131 #ifdef CONFIG_CPU_BIG_ENDIAN 132 unsigned int chip_id:16, cpu_id:8, family:8; 133 #else 134 unsigned int family:8, cpu_id:8, chip_id:16; 135 #endif 136 }; 137 138 struct bcr_isa { 139 #ifdef CONFIG_CPU_BIG_ENDIAN 140 unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1, 141 pad1:11, atomic1:1, ver:8; 142 #else 143 unsigned int ver:8, atomic1:1, pad1:11, be:1, atomic:1, unalign:1, 144 ldd:1, pad2:4, div_rem:4; 145 #endif 146 }; 147 148 struct bcr_mpy { 149 #ifdef CONFIG_CPU_BIG_ENDIAN 150 unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8; 151 #else 152 unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8; 153 #endif 154 }; 155 156 struct bcr_extn_xymem { 157 #ifdef CONFIG_CPU_BIG_ENDIAN 158 unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8; 159 #else 160 unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2; 161 #endif 162 }; 163 164 struct bcr_iccm_arcompact { 165 #ifdef CONFIG_CPU_BIG_ENDIAN 166 unsigned int base:16, pad:5, sz:3, ver:8; 167 #else 168 unsigned int ver:8, sz:3, pad:5, base:16; 169 #endif 170 }; 171 172 struct bcr_iccm_arcv2 { 173 #ifdef CONFIG_CPU_BIG_ENDIAN 174 unsigned int pad:8, sz11:4, sz01:4, sz10:4, sz00:4, ver:8; 175 #else 176 unsigned int ver:8, sz00:4, sz10:4, sz01:4, sz11:4, pad:8; 177 #endif 178 }; 179 180 struct bcr_dccm_arcompact { 181 #ifdef CONFIG_CPU_BIG_ENDIAN 182 unsigned int res:21, sz:3, ver:8; 183 #else 184 unsigned int ver:8, sz:3, res:21; 185 #endif 186 }; 187 188 struct bcr_dccm_arcv2 { 189 #ifdef CONFIG_CPU_BIG_ENDIAN 190 unsigned int pad2:12, cyc:3, pad1:1, sz1:4, sz0:4, ver:8; 191 #else 192 unsigned int ver:8, sz0:4, sz1:4, pad1:1, cyc:3, pad2:12; 193 #endif 194 }; 195 196 /* ARCompact: Both SP and DP FPU BCRs have same format */ 197 struct bcr_fp_arcompact { 198 #ifdef CONFIG_CPU_BIG_ENDIAN 199 unsigned int fast:1, ver:8; 200 #else 201 unsigned int ver:8, fast:1; 202 #endif 203 }; 204 205 struct bcr_fp_arcv2 { 206 #ifdef CONFIG_CPU_BIG_ENDIAN 207 unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8; 208 #else 209 unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15; 210 #endif 211 }; 212 213 #include <soc/arc/timers.h> 214 215 struct bcr_bpu_arcompact { 216 #ifdef CONFIG_CPU_BIG_ENDIAN 217 unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8; 218 #else 219 unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19; 220 #endif 221 }; 222 223 struct bcr_bpu_arcv2 { 224 #ifdef CONFIG_CPU_BIG_ENDIAN 225 unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8; 226 #else 227 unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6; 228 #endif 229 }; 230 231 struct bcr_generic { 232 #ifdef CONFIG_CPU_BIG_ENDIAN 233 unsigned int info:24, ver:8; 234 #else 235 unsigned int ver:8, info:24; 236 #endif 237 }; 238 239 /* 240 ******************************************************************* 241 * Generic structures to hold build configuration used at runtime 242 */ 243 244 struct cpuinfo_arc_mmu { 245 unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:10, sasid:1, pae:1; 246 unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8; 247 }; 248 249 struct cpuinfo_arc_cache { 250 unsigned int sz_k:14, line_len:8, assoc:4, alias:1, vipt:1, pad:4; 251 }; 252 253 struct cpuinfo_arc_bpu { 254 unsigned int ver, full, num_cache, num_pred; 255 }; 256 257 struct cpuinfo_arc_ccm { 258 unsigned int base_addr, sz; 259 }; 260 261 struct cpuinfo_arc { 262 struct cpuinfo_arc_cache icache, dcache, slc; 263 struct cpuinfo_arc_mmu mmu; 264 struct cpuinfo_arc_bpu bpu; 265 struct bcr_identity core; 266 struct bcr_isa isa; 267 const char *details, *name; 268 unsigned int vec_base; 269 struct cpuinfo_arc_ccm iccm, dccm; 270 struct { 271 unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2, 272 fpu_sp:1, fpu_dp:1, pad2:6, 273 debug:1, ap:1, smart:1, rtt:1, pad3:4, 274 timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4; 275 } extn; 276 struct bcr_mpy extn_mpy; 277 struct bcr_extn_xymem extn_xymem; 278 }; 279 280 extern struct cpuinfo_arc cpuinfo_arc700[]; 281 282 static inline int is_isa_arcv2(void) 283 { 284 return IS_ENABLED(CONFIG_ISA_ARCV2); 285 } 286 287 static inline int is_isa_arcompact(void) 288 { 289 return IS_ENABLED(CONFIG_ISA_ARCOMPACT); 290 } 291 292 #endif /* __ASEMBLY__ */ 293 294 #endif /* _ASM_ARC_ARCREGS_H */ 295