1 /* 2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #ifndef _ASM_ARC_ARCREGS_H 10 #define _ASM_ARC_ARCREGS_H 11 12 /* Build Configuration Registers */ 13 #define ARC_REG_DCCMBASE_BCR 0x61 /* DCCM Base Addr */ 14 #define ARC_REG_CRC_BCR 0x62 15 #define ARC_REG_VECBASE_BCR 0x68 16 #define ARC_REG_PERIBASE_BCR 0x69 17 #define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */ 18 #define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */ 19 #define ARC_REG_DCCM_BCR 0x74 /* DCCM Present + SZ */ 20 #define ARC_REG_TIMERS_BCR 0x75 21 #define ARC_REG_AP_BCR 0x76 22 #define ARC_REG_ICCM_BCR 0x78 23 #define ARC_REG_XY_MEM_BCR 0x79 24 #define ARC_REG_MAC_BCR 0x7a 25 #define ARC_REG_MUL_BCR 0x7b 26 #define ARC_REG_SWAP_BCR 0x7c 27 #define ARC_REG_NORM_BCR 0x7d 28 #define ARC_REG_MIXMAX_BCR 0x7e 29 #define ARC_REG_BARREL_BCR 0x7f 30 #define ARC_REG_D_UNCACH_BCR 0x6A 31 #define ARC_REG_BPU_BCR 0xc0 32 #define ARC_REG_ISA_CFG_BCR 0xc1 33 #define ARC_REG_RTT_BCR 0xF2 34 #define ARC_REG_SMART_BCR 0xFF 35 36 /* status32 Bits Positions */ 37 #define STATUS_AE_BIT 5 /* Exception active */ 38 #define STATUS_DE_BIT 6 /* PC is in delay slot */ 39 #define STATUS_U_BIT 7 /* User/Kernel mode */ 40 #define STATUS_L_BIT 12 /* Loop inhibit */ 41 42 /* These masks correspond to the status word(STATUS_32) bits */ 43 #define STATUS_AE_MASK (1<<STATUS_AE_BIT) 44 #define STATUS_DE_MASK (1<<STATUS_DE_BIT) 45 #define STATUS_U_MASK (1<<STATUS_U_BIT) 46 #define STATUS_L_MASK (1<<STATUS_L_BIT) 47 48 /* 49 * ECR: Exception Cause Reg bits-n-pieces 50 * [23:16] = Exception Vector 51 * [15: 8] = Exception Cause Code 52 * [ 7: 0] = Exception Parameters (for certain types only) 53 */ 54 #define ECR_V_MEM_ERR 0x01 55 #define ECR_V_INSN_ERR 0x02 56 #define ECR_V_MACH_CHK 0x20 57 #define ECR_V_ITLB_MISS 0x21 58 #define ECR_V_DTLB_MISS 0x22 59 #define ECR_V_PROTV 0x23 60 #define ECR_V_TRAP 0x25 61 62 /* DTLB Miss and Protection Violation Cause Codes */ 63 64 #define ECR_C_PROTV_INST_FETCH 0x00 65 #define ECR_C_PROTV_LOAD 0x01 66 #define ECR_C_PROTV_STORE 0x02 67 #define ECR_C_PROTV_XCHG 0x03 68 #define ECR_C_PROTV_MISALIG_DATA 0x04 69 70 #define ECR_C_BIT_PROTV_MISALIG_DATA 10 71 72 /* Machine Check Cause Code Values */ 73 #define ECR_C_MCHK_DUP_TLB 0x01 74 75 /* DTLB Miss Exception Cause Code Values */ 76 #define ECR_C_BIT_DTLB_LD_MISS 8 77 #define ECR_C_BIT_DTLB_ST_MISS 9 78 79 /* Dummy ECR values for Interrupts */ 80 #define event_IRQ1 0x0031abcd 81 #define event_IRQ2 0x0032abcd 82 83 /* Auxiliary registers */ 84 #define AUX_IDENTITY 4 85 #define AUX_INTR_VEC_BASE 0x25 86 87 88 /* 89 * Floating Pt Registers 90 * Status regs are read-only (build-time) so need not be saved/restored 91 */ 92 #define ARC_AUX_FP_STAT 0x300 93 #define ARC_AUX_DPFP_1L 0x301 94 #define ARC_AUX_DPFP_1H 0x302 95 #define ARC_AUX_DPFP_2L 0x303 96 #define ARC_AUX_DPFP_2H 0x304 97 #define ARC_AUX_DPFP_STAT 0x305 98 99 #ifndef __ASSEMBLY__ 100 101 /* 102 ****************************************************************** 103 * Inline ASM macros to read/write AUX Regs 104 * Essentially invocation of lr/sr insns from "C" 105 */ 106 107 #if 1 108 109 #define read_aux_reg(reg) __builtin_arc_lr(reg) 110 111 /* gcc builtin sr needs reg param to be long immediate */ 112 #define write_aux_reg(reg_immed, val) \ 113 __builtin_arc_sr((unsigned int)val, reg_immed) 114 115 #else 116 117 #define read_aux_reg(reg) \ 118 ({ \ 119 unsigned int __ret; \ 120 __asm__ __volatile__( \ 121 " lr %0, [%1]" \ 122 : "=r"(__ret) \ 123 : "i"(reg)); \ 124 __ret; \ 125 }) 126 127 /* 128 * Aux Reg address is specified as long immediate by caller 129 * e.g. 130 * write_aux_reg(0x69, some_val); 131 * This generates tightest code. 132 */ 133 #define write_aux_reg(reg_imm, val) \ 134 ({ \ 135 __asm__ __volatile__( \ 136 " sr %0, [%1] \n" \ 137 : \ 138 : "ir"(val), "i"(reg_imm)); \ 139 }) 140 141 /* 142 * Aux Reg address is specified in a variable 143 * * e.g. 144 * reg_num = 0x69 145 * write_aux_reg2(reg_num, some_val); 146 * This has to generate glue code to load the reg num from 147 * memory to a reg hence not recommended. 148 */ 149 #define write_aux_reg2(reg_in_var, val) \ 150 ({ \ 151 unsigned int tmp; \ 152 \ 153 __asm__ __volatile__( \ 154 " ld %0, [%2] \n\t" \ 155 " sr %1, [%0] \n\t" \ 156 : "=&r"(tmp) \ 157 : "r"(val), "memory"(®_in_var)); \ 158 }) 159 160 #endif 161 162 #define READ_BCR(reg, into) \ 163 { \ 164 unsigned int tmp; \ 165 tmp = read_aux_reg(reg); \ 166 if (sizeof(tmp) == sizeof(into)) { \ 167 into = *((typeof(into) *)&tmp); \ 168 } else { \ 169 extern void bogus_undefined(void); \ 170 bogus_undefined(); \ 171 } \ 172 } 173 174 #define WRITE_AUX(reg, into) \ 175 { \ 176 unsigned int tmp; \ 177 if (sizeof(tmp) == sizeof(into)) { \ 178 tmp = (*(unsigned int *)&(into)); \ 179 write_aux_reg(reg, tmp); \ 180 } else { \ 181 extern void bogus_undefined(void); \ 182 bogus_undefined(); \ 183 } \ 184 } 185 186 /* Helpers */ 187 #define TO_KB(bytes) ((bytes) >> 10) 188 #define TO_MB(bytes) (TO_KB(bytes) >> 10) 189 #define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10)) 190 #define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10) 191 192 193 /* 194 *************************************************************** 195 * Build Configuration Registers, with encoded hardware config 196 */ 197 struct bcr_identity { 198 #ifdef CONFIG_CPU_BIG_ENDIAN 199 unsigned int chip_id:16, cpu_id:8, family:8; 200 #else 201 unsigned int family:8, cpu_id:8, chip_id:16; 202 #endif 203 }; 204 205 struct bcr_isa { 206 #ifdef CONFIG_CPU_BIG_ENDIAN 207 unsigned int pad1:23, atomic1:1, ver:8; 208 #else 209 unsigned int ver:8, atomic1:1, pad1:23; 210 #endif 211 }; 212 213 struct bcr_mpy { 214 #ifdef CONFIG_CPU_BIG_ENDIAN 215 unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8; 216 #else 217 unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8; 218 #endif 219 }; 220 221 struct bcr_extn_xymem { 222 #ifdef CONFIG_CPU_BIG_ENDIAN 223 unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8; 224 #else 225 unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2; 226 #endif 227 }; 228 229 struct bcr_perip { 230 #ifdef CONFIG_CPU_BIG_ENDIAN 231 unsigned int start:8, pad2:8, sz:8, pad:8; 232 #else 233 unsigned int pad:8, sz:8, pad2:8, start:8; 234 #endif 235 }; 236 237 struct bcr_iccm { 238 #ifdef CONFIG_CPU_BIG_ENDIAN 239 unsigned int base:16, pad:5, sz:3, ver:8; 240 #else 241 unsigned int ver:8, sz:3, pad:5, base:16; 242 #endif 243 }; 244 245 /* DCCM Base Address Register: ARC_REG_DCCMBASE_BCR */ 246 struct bcr_dccm_base { 247 #ifdef CONFIG_CPU_BIG_ENDIAN 248 unsigned int addr:24, ver:8; 249 #else 250 unsigned int ver:8, addr:24; 251 #endif 252 }; 253 254 /* DCCM RAM Configuration Register: ARC_REG_DCCM_BCR */ 255 struct bcr_dccm { 256 #ifdef CONFIG_CPU_BIG_ENDIAN 257 unsigned int res:21, sz:3, ver:8; 258 #else 259 unsigned int ver:8, sz:3, res:21; 260 #endif 261 }; 262 263 /* ARCompact: Both SP and DP FPU BCRs have same format */ 264 struct bcr_fp_arcompact { 265 #ifdef CONFIG_CPU_BIG_ENDIAN 266 unsigned int fast:1, ver:8; 267 #else 268 unsigned int ver:8, fast:1; 269 #endif 270 }; 271 272 struct bcr_timer { 273 #ifdef CONFIG_CPU_BIG_ENDIAN 274 unsigned int pad2:15, rtsc:1, pad1:6, t1:1, t0:1, ver:8; 275 #else 276 unsigned int ver:8, t0:1, t1:1, pad1:6, rtsc:1, pad2:15; 277 #endif 278 }; 279 280 struct bcr_bpu_arcompact { 281 #ifdef CONFIG_CPU_BIG_ENDIAN 282 unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8; 283 #else 284 unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19; 285 #endif 286 }; 287 288 struct bcr_generic { 289 #ifdef CONFIG_CPU_BIG_ENDIAN 290 unsigned int pad:24, ver:8; 291 #else 292 unsigned int ver:8, pad:24; 293 #endif 294 }; 295 296 /* 297 ******************************************************************* 298 * Generic structures to hold build configuration used at runtime 299 */ 300 301 struct cpuinfo_arc_mmu { 302 unsigned int ver, pg_sz, sets, ways, u_dtlb, u_itlb, num_tlb; 303 }; 304 305 struct cpuinfo_arc_cache { 306 unsigned int sz_k:8, line_len:8, assoc:4, ver:4, alias:1, vipt:1, pad:6; 307 }; 308 309 struct cpuinfo_arc_bpu { 310 unsigned int ver, full, num_cache, num_pred; 311 }; 312 313 struct cpuinfo_arc_ccm { 314 unsigned int base_addr, sz; 315 }; 316 317 struct cpuinfo_arc { 318 struct cpuinfo_arc_cache icache, dcache; 319 struct cpuinfo_arc_mmu mmu; 320 struct cpuinfo_arc_bpu bpu; 321 struct bcr_identity core; 322 struct bcr_isa isa; 323 struct bcr_timer timers; 324 unsigned int vec_base; 325 unsigned int uncached_base; 326 struct cpuinfo_arc_ccm iccm, dccm; 327 struct { 328 unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, pad1:3, 329 fpu_sp:1, fpu_dp:1, pad2:6, 330 debug:1, ap:1, smart:1, rtt:1, pad3:4, 331 pad4:8; 332 } extn; 333 struct bcr_mpy extn_mpy; 334 struct bcr_extn_xymem extn_xymem; 335 }; 336 337 extern struct cpuinfo_arc cpuinfo_arc700[]; 338 339 #endif /* __ASEMBLY__ */ 340 341 #endif /* _ASM_ARC_ARCREGS_H */ 342