1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2ac4c244dSVineet Gupta /* 3ac4c244dSVineet Gupta * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 4ac4c244dSVineet Gupta */ 5ac4c244dSVineet Gupta 6ac4c244dSVineet Gupta #ifndef _ASM_ARC_ARCREGS_H 7ac4c244dSVineet Gupta #define _ASM_ARC_ARCREGS_H 8ac4c244dSVineet Gupta 9bacdf480SVineet Gupta /* Build Configuration Registers */ 10a150b085SVineet Gupta #define ARC_REG_AUX_DCCM 0x18 /* DCCM Base Addr ARCv2 */ 11f3156851SVineet Gupta #define ARC_REG_ERP_CTRL 0x3F /* ARCv2 Error protection control */ 12a150b085SVineet Gupta #define ARC_REG_DCCM_BASE_BUILD 0x61 /* DCCM Base Addr ARCompact */ 13af617428SVineet Gupta #define ARC_REG_CRC_BCR 0x62 14bacdf480SVineet Gupta #define ARC_REG_VECBASE_BCR 0x68 15af617428SVineet Gupta #define ARC_REG_PERIBASE_BCR 0x69 1656372082SVineet Gupta #define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */ 1756372082SVineet Gupta #define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */ 18f3156851SVineet Gupta #define ARC_REG_ERP_BUILD 0xc7 /* ARCv2 Error protection Build: ECC/Parity */ 191f6ccfffSVineet Gupta #define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */ 20d1f317d8SVineet Gupta #define ARC_REG_SLC_BCR 0xce 21a150b085SVineet Gupta #define ARC_REG_DCCM_BUILD 0x74 /* DCCM size (common) */ 2256372082SVineet Gupta #define ARC_REG_AP_BCR 0x76 23a150b085SVineet Gupta #define ARC_REG_ICCM_BUILD 0x78 /* ICCM size (common) */ 24af617428SVineet Gupta #define ARC_REG_XY_MEM_BCR 0x79 25af617428SVineet Gupta #define ARC_REG_MAC_BCR 0x7a 26af617428SVineet Gupta #define ARC_REG_MUL_BCR 0x7b 27af617428SVineet Gupta #define ARC_REG_SWAP_BCR 0x7c 28af617428SVineet Gupta #define ARC_REG_NORM_BCR 0x7d 29af617428SVineet Gupta #define ARC_REG_MIXMAX_BCR 0x7e 30af617428SVineet Gupta #define ARC_REG_BARREL_BCR 0x7f 31af617428SVineet Gupta #define ARC_REG_D_UNCACH_BCR 0x6A 3256372082SVineet Gupta #define ARC_REG_BPU_BCR 0xc0 3356372082SVineet Gupta #define ARC_REG_ISA_CFG_BCR 0xc1 34f3156851SVineet Gupta #define ARC_REG_LPB_BUILD 0xE9 /* ARCv2 Loop Buffer Build */ 35a44ec8bdSVineet Gupta #define ARC_REG_RTT_BCR 0xF2 36820970a5SVineet Gupta #define ARC_REG_IRQ_BCR 0xF3 37f3156851SVineet Gupta #define ARC_REG_MICRO_ARCH_BCR 0xF9 /* ARCv2 Product revision */ 3856372082SVineet Gupta #define ARC_REG_SMART_BCR 0xFF 39f2b0b25aSAlexey Brodkin #define ARC_REG_CLUSTER_BCR 0xcf 40a150b085SVineet Gupta #define ARC_REG_AUX_ICCM 0x208 /* ICCM Base Addr (ARCv2) */ 41f3156851SVineet Gupta #define ARC_REG_LPB_CTRL 0x488 /* ARCv2 Loop Buffer control */ 42bacdf480SVineet Gupta 43e98a7bf0SYuriy Kolerov /* Common for ARCompact and ARCv2 status register */ 44e98a7bf0SYuriy Kolerov #define ARC_REG_STATUS32 0x0A 45e98a7bf0SYuriy Kolerov 46ac4c244dSVineet Gupta /* status32 Bits Positions */ 47ac4c244dSVineet Gupta #define STATUS_AE_BIT 5 /* Exception active */ 48ac4c244dSVineet Gupta #define STATUS_DE_BIT 6 /* PC is in delay slot */ 49ac4c244dSVineet Gupta #define STATUS_U_BIT 7 /* User/Kernel mode */ 50e6e335bfSVineet Gupta #define STATUS_Z_BIT 11 51ac4c244dSVineet Gupta #define STATUS_L_BIT 12 /* Loop inhibit */ 52ac4c244dSVineet Gupta 53ac4c244dSVineet Gupta /* These masks correspond to the status word(STATUS_32) bits */ 54ac4c244dSVineet Gupta #define STATUS_AE_MASK (1<<STATUS_AE_BIT) 55ac4c244dSVineet Gupta #define STATUS_DE_MASK (1<<STATUS_DE_BIT) 56ac4c244dSVineet Gupta #define STATUS_U_MASK (1<<STATUS_U_BIT) 57e6e335bfSVineet Gupta #define STATUS_Z_MASK (1<<STATUS_Z_BIT) 58ac4c244dSVineet Gupta #define STATUS_L_MASK (1<<STATUS_L_BIT) 59ac4c244dSVineet Gupta 60cc562d2eSVineet Gupta /* 61cc562d2eSVineet Gupta * ECR: Exception Cause Reg bits-n-pieces 62cc562d2eSVineet Gupta * [23:16] = Exception Vector 63cc562d2eSVineet Gupta * [15: 8] = Exception Cause Code 64cc562d2eSVineet Gupta * [ 7: 0] = Exception Parameters (for certain types only) 65cc562d2eSVineet Gupta */ 661f6ccfffSVineet Gupta #ifdef CONFIG_ISA_ARCOMPACT 67dc9e234fSVineet Gupta #define ECR_V_MEM_ERR 0x01 68cc562d2eSVineet Gupta #define ECR_V_INSN_ERR 0x02 69cc562d2eSVineet Gupta #define ECR_V_MACH_CHK 0x20 70cc562d2eSVineet Gupta #define ECR_V_ITLB_MISS 0x21 71cc562d2eSVineet Gupta #define ECR_V_DTLB_MISS 0x22 72cc562d2eSVineet Gupta #define ECR_V_PROTV 0x23 73502a0c77SVineet Gupta #define ECR_V_TRAP 0x25 741f6ccfffSVineet Gupta #else 751f6ccfffSVineet Gupta #define ECR_V_MEM_ERR 0x01 761f6ccfffSVineet Gupta #define ECR_V_INSN_ERR 0x02 771f6ccfffSVineet Gupta #define ECR_V_MACH_CHK 0x03 781f6ccfffSVineet Gupta #define ECR_V_ITLB_MISS 0x04 791f6ccfffSVineet Gupta #define ECR_V_DTLB_MISS 0x05 801f6ccfffSVineet Gupta #define ECR_V_PROTV 0x06 811f6ccfffSVineet Gupta #define ECR_V_TRAP 0x09 8276551468SEugeniy Paltsev #define ECR_V_MISALIGN 0x0d 831f6ccfffSVineet Gupta #endif 84cc562d2eSVineet Gupta 85dc9e234fSVineet Gupta /* DTLB Miss and Protection Violation Cause Codes */ 86dc9e234fSVineet Gupta 87cc562d2eSVineet Gupta #define ECR_C_PROTV_INST_FETCH 0x00 88cc562d2eSVineet Gupta #define ECR_C_PROTV_LOAD 0x01 89cc562d2eSVineet Gupta #define ECR_C_PROTV_STORE 0x02 90cc562d2eSVineet Gupta #define ECR_C_PROTV_XCHG 0x03 91cc562d2eSVineet Gupta #define ECR_C_PROTV_MISALIG_DATA 0x04 92cc562d2eSVineet Gupta 931898a959SVineet Gupta #define ECR_C_BIT_PROTV_MISALIG_DATA 10 941898a959SVineet Gupta 951898a959SVineet Gupta /* Machine Check Cause Code Values */ 961898a959SVineet Gupta #define ECR_C_MCHK_DUP_TLB 0x01 971898a959SVineet Gupta 98cc562d2eSVineet Gupta /* DTLB Miss Exception Cause Code Values */ 99cc562d2eSVineet Gupta #define ECR_C_BIT_DTLB_LD_MISS 8 100cc562d2eSVineet Gupta #define ECR_C_BIT_DTLB_ST_MISS 9 101cc562d2eSVineet Gupta 102ac4c244dSVineet Gupta /* Auxiliary registers */ 103ac4c244dSVineet Gupta #define AUX_IDENTITY 4 104dea82520SVineet Gupta #define AUX_EXEC_CTRL 8 105ac4c244dSVineet Gupta #define AUX_INTR_VEC_BASE 0x25 10626c01c49SVineet Gupta #define AUX_VOL 0x5e 107f1f3347dSVineet Gupta 108bf90e1eaSVineet Gupta /* 109bf90e1eaSVineet Gupta * Floating Pt Registers 110bf90e1eaSVineet Gupta * Status regs are read-only (build-time) so need not be saved/restored 111bf90e1eaSVineet Gupta */ 112bf90e1eaSVineet Gupta #define ARC_AUX_FP_STAT 0x300 113bf90e1eaSVineet Gupta #define ARC_AUX_DPFP_1L 0x301 114bf90e1eaSVineet Gupta #define ARC_AUX_DPFP_1H 0x302 115bf90e1eaSVineet Gupta #define ARC_AUX_DPFP_2L 0x303 116bf90e1eaSVineet Gupta #define ARC_AUX_DPFP_2H 0x304 117bf90e1eaSVineet Gupta #define ARC_AUX_DPFP_STAT 0x305 118bf90e1eaSVineet Gupta 119ac4c244dSVineet Gupta #ifndef __ASSEMBLY__ 120ac4c244dSVineet Gupta 121c33a605dSVineet Gupta #include <soc/arc/aux.h> 12295d6976dSVineet Gupta 123c121c506SVineet Gupta /* Helpers */ 124c121c506SVineet Gupta #define TO_KB(bytes) ((bytes) >> 10) 125c121c506SVineet Gupta #define TO_MB(bytes) (TO_KB(bytes) >> 10) 126c121c506SVineet Gupta #define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10)) 127c121c506SVineet Gupta #define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10) 12895d6976dSVineet Gupta 129bf90e1eaSVineet Gupta 13095d6976dSVineet Gupta /* 13195d6976dSVineet Gupta *************************************************************** 13295d6976dSVineet Gupta * Build Configuration Registers, with encoded hardware config 13395d6976dSVineet Gupta */ 134af617428SVineet Gupta struct bcr_identity { 135af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 136af617428SVineet Gupta unsigned int chip_id:16, cpu_id:8, family:8; 137af617428SVineet Gupta #else 138af617428SVineet Gupta unsigned int family:8, cpu_id:8, chip_id:16; 139af617428SVineet Gupta #endif 140af617428SVineet Gupta }; 14195d6976dSVineet Gupta 142010a8c98SVineet Gupta struct bcr_isa_arcv2 { 143af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 1441f6ccfffSVineet Gupta unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1, 145010a8c98SVineet Gupta pad1:12, ver:8; 146af617428SVineet Gupta #else 147010a8c98SVineet Gupta unsigned int ver:8, pad1:12, be:1, atomic:1, unalign:1, 1481f6ccfffSVineet Gupta ldd:1, pad2:4, div_rem:4; 149af617428SVineet Gupta #endif 150af617428SVineet Gupta }; 151af617428SVineet Gupta 1527b2e932fSVineet Gupta struct bcr_uarch_build_arcv2 { 1537b2e932fSVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 1547b2e932fSVineet Gupta unsigned int pad:8, prod:8, maj:8, min:8; 1557b2e932fSVineet Gupta #else 1567b2e932fSVineet Gupta unsigned int min:8, maj:8, prod:8, pad:8; 1577b2e932fSVineet Gupta #endif 1587b2e932fSVineet Gupta }; 1597b2e932fSVineet Gupta 16056372082SVineet Gupta struct bcr_mpy { 161af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 16256372082SVineet Gupta unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8; 163af617428SVineet Gupta #else 16456372082SVineet Gupta unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8; 165af617428SVineet Gupta #endif 166af617428SVineet Gupta }; 167af617428SVineet Gupta 168a150b085SVineet Gupta struct bcr_iccm_arcompact { 169af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 170af617428SVineet Gupta unsigned int base:16, pad:5, sz:3, ver:8; 171af617428SVineet Gupta #else 172af617428SVineet Gupta unsigned int ver:8, sz:3, pad:5, base:16; 173af617428SVineet Gupta #endif 174af617428SVineet Gupta }; 175af617428SVineet Gupta 176a150b085SVineet Gupta struct bcr_iccm_arcv2 { 177af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 178a150b085SVineet Gupta unsigned int pad:8, sz11:4, sz01:4, sz10:4, sz00:4, ver:8; 179af617428SVineet Gupta #else 180a150b085SVineet Gupta unsigned int ver:8, sz00:4, sz10:4, sz01:4, sz11:4, pad:8; 181af617428SVineet Gupta #endif 182af617428SVineet Gupta }; 183af617428SVineet Gupta 184a150b085SVineet Gupta struct bcr_dccm_arcompact { 185af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 186af617428SVineet Gupta unsigned int res:21, sz:3, ver:8; 187af617428SVineet Gupta #else 188af617428SVineet Gupta unsigned int ver:8, sz:3, res:21; 189af617428SVineet Gupta #endif 190af617428SVineet Gupta }; 191af617428SVineet Gupta 192a150b085SVineet Gupta struct bcr_dccm_arcv2 { 193a150b085SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 194a150b085SVineet Gupta unsigned int pad2:12, cyc:3, pad1:1, sz1:4, sz0:4, ver:8; 195a150b085SVineet Gupta #else 196a150b085SVineet Gupta unsigned int ver:8, sz0:4, sz1:4, pad1:1, cyc:3, pad2:12; 197a150b085SVineet Gupta #endif 198a150b085SVineet Gupta }; 199a150b085SVineet Gupta 20056372082SVineet Gupta /* ARCompact: Both SP and DP FPU BCRs have same format */ 20156372082SVineet Gupta struct bcr_fp_arcompact { 202af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 203af617428SVineet Gupta unsigned int fast:1, ver:8; 204af617428SVineet Gupta #else 205af617428SVineet Gupta unsigned int ver:8, fast:1; 206af617428SVineet Gupta #endif 207af617428SVineet Gupta }; 208af617428SVineet Gupta 2091f6ccfffSVineet Gupta struct bcr_fp_arcv2 { 2101f6ccfffSVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 2111f6ccfffSVineet Gupta unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8; 2121f6ccfffSVineet Gupta #else 2131f6ccfffSVineet Gupta unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15; 2141f6ccfffSVineet Gupta #endif 2151f6ccfffSVineet Gupta }; 2161f6ccfffSVineet Gupta 2177dd380c3SVineet Gupta struct bcr_actionpoint { 2187dd380c3SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 2197dd380c3SVineet Gupta unsigned int pad:21, min:1, num:2, ver:8; 2207dd380c3SVineet Gupta #else 2217dd380c3SVineet Gupta unsigned int ver:8, num:2, min:1, pad:21; 2227dd380c3SVineet Gupta #endif 2237dd380c3SVineet Gupta }; 2247dd380c3SVineet Gupta 225b26c2e38SVineet Gupta #include <soc/arc/timers.h> 22656372082SVineet Gupta 22756372082SVineet Gupta struct bcr_bpu_arcompact { 22856372082SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 22956372082SVineet Gupta unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8; 23056372082SVineet Gupta #else 23156372082SVineet Gupta unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19; 23256372082SVineet Gupta #endif 23356372082SVineet Gupta }; 23456372082SVineet Gupta 2351f6ccfffSVineet Gupta struct bcr_bpu_arcv2 { 2361f6ccfffSVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 2371f6ccfffSVineet Gupta unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8; 2381f6ccfffSVineet Gupta #else 2391f6ccfffSVineet Gupta unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6; 2401f6ccfffSVineet Gupta #endif 2411f6ccfffSVineet Gupta }; 2421f6ccfffSVineet Gupta 243f3156851SVineet Gupta /* Error Protection Build: ECC/Parity */ 244f3156851SVineet Gupta struct bcr_erp { 245f3156851SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 246f3156851SVineet Gupta unsigned int pad3:5, mmu:3, pad2:4, ic:3, dc:3, pad1:6, ver:8; 247f3156851SVineet Gupta #else 248f3156851SVineet Gupta unsigned int ver:8, pad1:6, dc:3, ic:3, pad2:4, mmu:3, pad3:5; 249f3156851SVineet Gupta #endif 250f3156851SVineet Gupta }; 251f3156851SVineet Gupta 252f3156851SVineet Gupta /* Error Protection Control */ 253f3156851SVineet Gupta struct ctl_erp { 254f3156851SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 255f3156851SVineet Gupta unsigned int pad2:27, mpd:1, pad1:2, dpd:1, dpi:1; 256f3156851SVineet Gupta #else 257f3156851SVineet Gupta unsigned int dpi:1, dpd:1, pad1:2, mpd:1, pad2:27; 258f3156851SVineet Gupta #endif 259f3156851SVineet Gupta }; 260f3156851SVineet Gupta 261f3156851SVineet Gupta struct bcr_lpb { 262f3156851SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 263f3156851SVineet Gupta unsigned int pad:16, entries:8, ver:8; 264f3156851SVineet Gupta #else 265f3156851SVineet Gupta unsigned int ver:8, entries:8, pad:16; 266f3156851SVineet Gupta #endif 267f3156851SVineet Gupta }; 268f3156851SVineet Gupta 26956372082SVineet Gupta struct bcr_generic { 27056372082SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 271a150b085SVineet Gupta unsigned int info:24, ver:8; 27256372082SVineet Gupta #else 273a150b085SVineet Gupta unsigned int ver:8, info:24; 27456372082SVineet Gupta #endif 27556372082SVineet Gupta }; 27656372082SVineet Gupta 27795d6976dSVineet Gupta /* 27895d6976dSVineet Gupta ******************************************************************* 27995d6976dSVineet Gupta * Generic structures to hold build configuration used at runtime 28095d6976dSVineet Gupta */ 28195d6976dSVineet Gupta 282cc562d2eSVineet Gupta struct cpuinfo_arc_mmu { 283d0890ea5SVineet Gupta unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:10, sasid:1, pae:1; 284b598e17fSVineet Gupta unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8; 285cc562d2eSVineet Gupta }; 286cc562d2eSVineet Gupta 28795d6976dSVineet Gupta struct cpuinfo_arc_cache { 288f64915beSVineet Gupta unsigned int sz_k:14, line_len:8, assoc:4, alias:1, vipt:1, pad:4; 28995d6976dSVineet Gupta }; 29095d6976dSVineet Gupta 29156372082SVineet Gupta struct cpuinfo_arc_bpu { 29297e98132SVineet Gupta unsigned int ver, full, num_cache, num_pred, ret_stk; 29356372082SVineet Gupta }; 29456372082SVineet Gupta 295af617428SVineet Gupta struct cpuinfo_arc_ccm { 296af617428SVineet Gupta unsigned int base_addr, sz; 297af617428SVineet Gupta }; 298af617428SVineet Gupta 29995d6976dSVineet Gupta struct cpuinfo_arc { 300d1f317d8SVineet Gupta struct cpuinfo_arc_cache icache, dcache, slc; 301cc562d2eSVineet Gupta struct cpuinfo_arc_mmu mmu; 30256372082SVineet Gupta struct cpuinfo_arc_bpu bpu; 303af617428SVineet Gupta struct bcr_identity core; 304010a8c98SVineet Gupta struct bcr_isa_arcv2 isa; 30500a4ae65SVineet Gupta const char *release, *name; 306af617428SVineet Gupta unsigned int vec_base; 307af617428SVineet Gupta struct cpuinfo_arc_ccm iccm, dccm; 30856372082SVineet Gupta struct { 309a024fd9bSVineet Gupta unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2, 310f3156851SVineet Gupta fpu_sp:1, fpu_dp:1, dual:1, dual_enb:1, pad2:4, 3117dd380c3SVineet Gupta ap_num:4, ap_full:1, smart:1, rtt:1, pad3:1, 312b89bd1f4SVineet Gupta timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4; 31356372082SVineet Gupta } extn; 31456372082SVineet Gupta struct bcr_mpy extn_mpy; 31595d6976dSVineet Gupta }; 31695d6976dSVineet Gupta 31795d6976dSVineet Gupta extern struct cpuinfo_arc cpuinfo_arc700[]; 31895d6976dSVineet Gupta 3191f6ccfffSVineet Gupta static inline int is_isa_arcv2(void) 3201f6ccfffSVineet Gupta { 3211f6ccfffSVineet Gupta return IS_ENABLED(CONFIG_ISA_ARCV2); 3221f6ccfffSVineet Gupta } 3231f6ccfffSVineet Gupta 3241f6ccfffSVineet Gupta static inline int is_isa_arcompact(void) 3251f6ccfffSVineet Gupta { 3261f6ccfffSVineet Gupta return IS_ENABLED(CONFIG_ISA_ARCOMPACT); 3271f6ccfffSVineet Gupta } 3281f6ccfffSVineet Gupta 329ac4c244dSVineet Gupta #endif /* __ASEMBLY__ */ 330ac4c244dSVineet Gupta 331ac4c244dSVineet Gupta #endif /* _ASM_ARC_ARCREGS_H */ 332