1ac4c244dSVineet Gupta /* 2ac4c244dSVineet Gupta * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3ac4c244dSVineet Gupta * 4ac4c244dSVineet Gupta * This program is free software; you can redistribute it and/or modify 5ac4c244dSVineet Gupta * it under the terms of the GNU General Public License version 2 as 6ac4c244dSVineet Gupta * published by the Free Software Foundation. 7ac4c244dSVineet Gupta */ 8ac4c244dSVineet Gupta 9ac4c244dSVineet Gupta #ifndef _ASM_ARC_ARCREGS_H 10ac4c244dSVineet Gupta #define _ASM_ARC_ARCREGS_H 11ac4c244dSVineet Gupta 12bacdf480SVineet Gupta /* Build Configuration Registers */ 13a150b085SVineet Gupta #define ARC_REG_AUX_DCCM 0x18 /* DCCM Base Addr ARCv2 */ 14a150b085SVineet Gupta #define ARC_REG_DCCM_BASE_BUILD 0x61 /* DCCM Base Addr ARCompact */ 15af617428SVineet Gupta #define ARC_REG_CRC_BCR 0x62 16bacdf480SVineet Gupta #define ARC_REG_VECBASE_BCR 0x68 17af617428SVineet Gupta #define ARC_REG_PERIBASE_BCR 0x69 1856372082SVineet Gupta #define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */ 1956372082SVineet Gupta #define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */ 201f6ccfffSVineet Gupta #define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */ 21d1f317d8SVineet Gupta #define ARC_REG_SLC_BCR 0xce 22a150b085SVineet Gupta #define ARC_REG_DCCM_BUILD 0x74 /* DCCM size (common) */ 23af617428SVineet Gupta #define ARC_REG_TIMERS_BCR 0x75 2456372082SVineet Gupta #define ARC_REG_AP_BCR 0x76 25a150b085SVineet Gupta #define ARC_REG_ICCM_BUILD 0x78 /* ICCM size (common) */ 26af617428SVineet Gupta #define ARC_REG_XY_MEM_BCR 0x79 27af617428SVineet Gupta #define ARC_REG_MAC_BCR 0x7a 28af617428SVineet Gupta #define ARC_REG_MUL_BCR 0x7b 29af617428SVineet Gupta #define ARC_REG_SWAP_BCR 0x7c 30af617428SVineet Gupta #define ARC_REG_NORM_BCR 0x7d 31af617428SVineet Gupta #define ARC_REG_MIXMAX_BCR 0x7e 32af617428SVineet Gupta #define ARC_REG_BARREL_BCR 0x7f 33af617428SVineet Gupta #define ARC_REG_D_UNCACH_BCR 0x6A 3456372082SVineet Gupta #define ARC_REG_BPU_BCR 0xc0 3556372082SVineet Gupta #define ARC_REG_ISA_CFG_BCR 0xc1 36a44ec8bdSVineet Gupta #define ARC_REG_RTT_BCR 0xF2 37820970a5SVineet Gupta #define ARC_REG_IRQ_BCR 0xF3 3856372082SVineet Gupta #define ARC_REG_SMART_BCR 0xFF 39f2b0b25aSAlexey Brodkin #define ARC_REG_CLUSTER_BCR 0xcf 40a150b085SVineet Gupta #define ARC_REG_AUX_ICCM 0x208 /* ICCM Base Addr (ARCv2) */ 41bacdf480SVineet Gupta 42ac4c244dSVineet Gupta /* status32 Bits Positions */ 43ac4c244dSVineet Gupta #define STATUS_AE_BIT 5 /* Exception active */ 44ac4c244dSVineet Gupta #define STATUS_DE_BIT 6 /* PC is in delay slot */ 45ac4c244dSVineet Gupta #define STATUS_U_BIT 7 /* User/Kernel mode */ 46ac4c244dSVineet Gupta #define STATUS_L_BIT 12 /* Loop inhibit */ 47ac4c244dSVineet Gupta 48ac4c244dSVineet Gupta /* These masks correspond to the status word(STATUS_32) bits */ 49ac4c244dSVineet Gupta #define STATUS_AE_MASK (1<<STATUS_AE_BIT) 50ac4c244dSVineet Gupta #define STATUS_DE_MASK (1<<STATUS_DE_BIT) 51ac4c244dSVineet Gupta #define STATUS_U_MASK (1<<STATUS_U_BIT) 52ac4c244dSVineet Gupta #define STATUS_L_MASK (1<<STATUS_L_BIT) 53ac4c244dSVineet Gupta 54cc562d2eSVineet Gupta /* 55cc562d2eSVineet Gupta * ECR: Exception Cause Reg bits-n-pieces 56cc562d2eSVineet Gupta * [23:16] = Exception Vector 57cc562d2eSVineet Gupta * [15: 8] = Exception Cause Code 58cc562d2eSVineet Gupta * [ 7: 0] = Exception Parameters (for certain types only) 59cc562d2eSVineet Gupta */ 601f6ccfffSVineet Gupta #ifdef CONFIG_ISA_ARCOMPACT 61dc9e234fSVineet Gupta #define ECR_V_MEM_ERR 0x01 62cc562d2eSVineet Gupta #define ECR_V_INSN_ERR 0x02 63cc562d2eSVineet Gupta #define ECR_V_MACH_CHK 0x20 64cc562d2eSVineet Gupta #define ECR_V_ITLB_MISS 0x21 65cc562d2eSVineet Gupta #define ECR_V_DTLB_MISS 0x22 66cc562d2eSVineet Gupta #define ECR_V_PROTV 0x23 67502a0c77SVineet Gupta #define ECR_V_TRAP 0x25 681f6ccfffSVineet Gupta #else 691f6ccfffSVineet Gupta #define ECR_V_MEM_ERR 0x01 701f6ccfffSVineet Gupta #define ECR_V_INSN_ERR 0x02 711f6ccfffSVineet Gupta #define ECR_V_MACH_CHK 0x03 721f6ccfffSVineet Gupta #define ECR_V_ITLB_MISS 0x04 731f6ccfffSVineet Gupta #define ECR_V_DTLB_MISS 0x05 741f6ccfffSVineet Gupta #define ECR_V_PROTV 0x06 751f6ccfffSVineet Gupta #define ECR_V_TRAP 0x09 761f6ccfffSVineet Gupta #endif 77cc562d2eSVineet Gupta 78dc9e234fSVineet Gupta /* DTLB Miss and Protection Violation Cause Codes */ 79dc9e234fSVineet Gupta 80cc562d2eSVineet Gupta #define ECR_C_PROTV_INST_FETCH 0x00 81cc562d2eSVineet Gupta #define ECR_C_PROTV_LOAD 0x01 82cc562d2eSVineet Gupta #define ECR_C_PROTV_STORE 0x02 83cc562d2eSVineet Gupta #define ECR_C_PROTV_XCHG 0x03 84cc562d2eSVineet Gupta #define ECR_C_PROTV_MISALIG_DATA 0x04 85cc562d2eSVineet Gupta 861898a959SVineet Gupta #define ECR_C_BIT_PROTV_MISALIG_DATA 10 871898a959SVineet Gupta 881898a959SVineet Gupta /* Machine Check Cause Code Values */ 891898a959SVineet Gupta #define ECR_C_MCHK_DUP_TLB 0x01 901898a959SVineet Gupta 91cc562d2eSVineet Gupta /* DTLB Miss Exception Cause Code Values */ 92cc562d2eSVineet Gupta #define ECR_C_BIT_DTLB_LD_MISS 8 93cc562d2eSVineet Gupta #define ECR_C_BIT_DTLB_ST_MISS 9 94cc562d2eSVineet Gupta 95ac4c244dSVineet Gupta /* Auxiliary registers */ 96ac4c244dSVineet Gupta #define AUX_IDENTITY 4 97ac4c244dSVineet Gupta #define AUX_INTR_VEC_BASE 0x25 9826c01c49SVineet Gupta #define AUX_VOL 0x5e 99f1f3347dSVineet Gupta 100bf90e1eaSVineet Gupta /* 101bf90e1eaSVineet Gupta * Floating Pt Registers 102bf90e1eaSVineet Gupta * Status regs are read-only (build-time) so need not be saved/restored 103bf90e1eaSVineet Gupta */ 104bf90e1eaSVineet Gupta #define ARC_AUX_FP_STAT 0x300 105bf90e1eaSVineet Gupta #define ARC_AUX_DPFP_1L 0x301 106bf90e1eaSVineet Gupta #define ARC_AUX_DPFP_1H 0x302 107bf90e1eaSVineet Gupta #define ARC_AUX_DPFP_2L 0x303 108bf90e1eaSVineet Gupta #define ARC_AUX_DPFP_2H 0x304 109bf90e1eaSVineet Gupta #define ARC_AUX_DPFP_STAT 0x305 110bf90e1eaSVineet Gupta 111ac4c244dSVineet Gupta #ifndef __ASSEMBLY__ 112ac4c244dSVineet Gupta 113ac4c244dSVineet Gupta /* 114ac4c244dSVineet Gupta ****************************************************************** 115ac4c244dSVineet Gupta * Inline ASM macros to read/write AUX Regs 116ac4c244dSVineet Gupta * Essentially invocation of lr/sr insns from "C" 117ac4c244dSVineet Gupta */ 118ac4c244dSVineet Gupta 119ac4c244dSVineet Gupta #if 1 120ac4c244dSVineet Gupta 121ac4c244dSVineet Gupta #define read_aux_reg(reg) __builtin_arc_lr(reg) 122ac4c244dSVineet Gupta 123ac4c244dSVineet Gupta /* gcc builtin sr needs reg param to be long immediate */ 124ac4c244dSVineet Gupta #define write_aux_reg(reg_immed, val) \ 1255c35ee64SVineet Gupta __builtin_arc_sr((unsigned int)(val), reg_immed) 126ac4c244dSVineet Gupta 127ac4c244dSVineet Gupta #else 128ac4c244dSVineet Gupta 129ac4c244dSVineet Gupta #define read_aux_reg(reg) \ 130ac4c244dSVineet Gupta ({ \ 131ac4c244dSVineet Gupta unsigned int __ret; \ 132ac4c244dSVineet Gupta __asm__ __volatile__( \ 133ac4c244dSVineet Gupta " lr %0, [%1]" \ 134ac4c244dSVineet Gupta : "=r"(__ret) \ 135ac4c244dSVineet Gupta : "i"(reg)); \ 136ac4c244dSVineet Gupta __ret; \ 137ac4c244dSVineet Gupta }) 138ac4c244dSVineet Gupta 139ac4c244dSVineet Gupta /* 140ac4c244dSVineet Gupta * Aux Reg address is specified as long immediate by caller 141ac4c244dSVineet Gupta * e.g. 142ac4c244dSVineet Gupta * write_aux_reg(0x69, some_val); 143ac4c244dSVineet Gupta * This generates tightest code. 144ac4c244dSVineet Gupta */ 145ac4c244dSVineet Gupta #define write_aux_reg(reg_imm, val) \ 146ac4c244dSVineet Gupta ({ \ 147ac4c244dSVineet Gupta __asm__ __volatile__( \ 148ac4c244dSVineet Gupta " sr %0, [%1] \n" \ 149ac4c244dSVineet Gupta : \ 150ac4c244dSVineet Gupta : "ir"(val), "i"(reg_imm)); \ 151ac4c244dSVineet Gupta }) 152ac4c244dSVineet Gupta 153ac4c244dSVineet Gupta /* 154ac4c244dSVineet Gupta * Aux Reg address is specified in a variable 155ac4c244dSVineet Gupta * * e.g. 156ac4c244dSVineet Gupta * reg_num = 0x69 157ac4c244dSVineet Gupta * write_aux_reg2(reg_num, some_val); 158ac4c244dSVineet Gupta * This has to generate glue code to load the reg num from 159ac4c244dSVineet Gupta * memory to a reg hence not recommended. 160ac4c244dSVineet Gupta */ 161ac4c244dSVineet Gupta #define write_aux_reg2(reg_in_var, val) \ 162ac4c244dSVineet Gupta ({ \ 163ac4c244dSVineet Gupta unsigned int tmp; \ 164ac4c244dSVineet Gupta \ 165ac4c244dSVineet Gupta __asm__ __volatile__( \ 166ac4c244dSVineet Gupta " ld %0, [%2] \n\t" \ 167ac4c244dSVineet Gupta " sr %1, [%0] \n\t" \ 168ac4c244dSVineet Gupta : "=&r"(tmp) \ 169ac4c244dSVineet Gupta : "r"(val), "memory"(®_in_var)); \ 170ac4c244dSVineet Gupta }) 171ac4c244dSVineet Gupta 172ac4c244dSVineet Gupta #endif 173ac4c244dSVineet Gupta 17495d6976dSVineet Gupta #define READ_BCR(reg, into) \ 17595d6976dSVineet Gupta { \ 17695d6976dSVineet Gupta unsigned int tmp; \ 17795d6976dSVineet Gupta tmp = read_aux_reg(reg); \ 17895d6976dSVineet Gupta if (sizeof(tmp) == sizeof(into)) { \ 17995d6976dSVineet Gupta into = *((typeof(into) *)&tmp); \ 18095d6976dSVineet Gupta } else { \ 18195d6976dSVineet Gupta extern void bogus_undefined(void); \ 18295d6976dSVineet Gupta bogus_undefined(); \ 18395d6976dSVineet Gupta } \ 18495d6976dSVineet Gupta } 18595d6976dSVineet Gupta 1861425d5e7SVineet Gupta #define WRITE_AUX(reg, into) \ 18795d6976dSVineet Gupta { \ 18895d6976dSVineet Gupta unsigned int tmp; \ 18995d6976dSVineet Gupta if (sizeof(tmp) == sizeof(into)) { \ 1901425d5e7SVineet Gupta tmp = (*(unsigned int *)&(into)); \ 19195d6976dSVineet Gupta write_aux_reg(reg, tmp); \ 19295d6976dSVineet Gupta } else { \ 19395d6976dSVineet Gupta extern void bogus_undefined(void); \ 19495d6976dSVineet Gupta bogus_undefined(); \ 19595d6976dSVineet Gupta } \ 19695d6976dSVineet Gupta } 19795d6976dSVineet Gupta 198c121c506SVineet Gupta /* Helpers */ 199c121c506SVineet Gupta #define TO_KB(bytes) ((bytes) >> 10) 200c121c506SVineet Gupta #define TO_MB(bytes) (TO_KB(bytes) >> 10) 201c121c506SVineet Gupta #define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10)) 202c121c506SVineet Gupta #define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10) 20395d6976dSVineet Gupta 204bf90e1eaSVineet Gupta 20595d6976dSVineet Gupta /* 20695d6976dSVineet Gupta *************************************************************** 20795d6976dSVineet Gupta * Build Configuration Registers, with encoded hardware config 20895d6976dSVineet Gupta */ 209af617428SVineet Gupta struct bcr_identity { 210af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 211af617428SVineet Gupta unsigned int chip_id:16, cpu_id:8, family:8; 212af617428SVineet Gupta #else 213af617428SVineet Gupta unsigned int family:8, cpu_id:8, chip_id:16; 214af617428SVineet Gupta #endif 215af617428SVineet Gupta }; 21695d6976dSVineet Gupta 21756372082SVineet Gupta struct bcr_isa { 218af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 2191f6ccfffSVineet Gupta unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1, 2201f6ccfffSVineet Gupta pad1:11, atomic1:1, ver:8; 221af617428SVineet Gupta #else 2221f6ccfffSVineet Gupta unsigned int ver:8, atomic1:1, pad1:11, be:1, atomic:1, unalign:1, 2231f6ccfffSVineet Gupta ldd:1, pad2:4, div_rem:4; 224af617428SVineet Gupta #endif 225af617428SVineet Gupta }; 226af617428SVineet Gupta 22756372082SVineet Gupta struct bcr_mpy { 228af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 22956372082SVineet Gupta unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8; 230af617428SVineet Gupta #else 23156372082SVineet Gupta unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8; 232af617428SVineet Gupta #endif 233af617428SVineet Gupta }; 234af617428SVineet Gupta 235af617428SVineet Gupta struct bcr_extn_xymem { 236af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 237af617428SVineet Gupta unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8; 238af617428SVineet Gupta #else 239af617428SVineet Gupta unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2; 240af617428SVineet Gupta #endif 241af617428SVineet Gupta }; 242af617428SVineet Gupta 243a150b085SVineet Gupta struct bcr_iccm_arcompact { 244af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 245af617428SVineet Gupta unsigned int base:16, pad:5, sz:3, ver:8; 246af617428SVineet Gupta #else 247af617428SVineet Gupta unsigned int ver:8, sz:3, pad:5, base:16; 248af617428SVineet Gupta #endif 249af617428SVineet Gupta }; 250af617428SVineet Gupta 251a150b085SVineet Gupta struct bcr_iccm_arcv2 { 252af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 253a150b085SVineet Gupta unsigned int pad:8, sz11:4, sz01:4, sz10:4, sz00:4, ver:8; 254af617428SVineet Gupta #else 255a150b085SVineet Gupta unsigned int ver:8, sz00:4, sz10:4, sz01:4, sz11:4, pad:8; 256af617428SVineet Gupta #endif 257af617428SVineet Gupta }; 258af617428SVineet Gupta 259a150b085SVineet Gupta struct bcr_dccm_arcompact { 260af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 261af617428SVineet Gupta unsigned int res:21, sz:3, ver:8; 262af617428SVineet Gupta #else 263af617428SVineet Gupta unsigned int ver:8, sz:3, res:21; 264af617428SVineet Gupta #endif 265af617428SVineet Gupta }; 266af617428SVineet Gupta 267a150b085SVineet Gupta struct bcr_dccm_arcv2 { 268a150b085SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 269a150b085SVineet Gupta unsigned int pad2:12, cyc:3, pad1:1, sz1:4, sz0:4, ver:8; 270a150b085SVineet Gupta #else 271a150b085SVineet Gupta unsigned int ver:8, sz0:4, sz1:4, pad1:1, cyc:3, pad2:12; 272a150b085SVineet Gupta #endif 273a150b085SVineet Gupta }; 274a150b085SVineet Gupta 27556372082SVineet Gupta /* ARCompact: Both SP and DP FPU BCRs have same format */ 27656372082SVineet Gupta struct bcr_fp_arcompact { 277af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 278af617428SVineet Gupta unsigned int fast:1, ver:8; 279af617428SVineet Gupta #else 280af617428SVineet Gupta unsigned int ver:8, fast:1; 281af617428SVineet Gupta #endif 282af617428SVineet Gupta }; 283af617428SVineet Gupta 2841f6ccfffSVineet Gupta struct bcr_fp_arcv2 { 2851f6ccfffSVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 2861f6ccfffSVineet Gupta unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8; 2871f6ccfffSVineet Gupta #else 2881f6ccfffSVineet Gupta unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15; 2891f6ccfffSVineet Gupta #endif 2901f6ccfffSVineet Gupta }; 2911f6ccfffSVineet Gupta 29256372082SVineet Gupta struct bcr_timer { 29356372082SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 2941f6ccfffSVineet Gupta unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8; 29556372082SVineet Gupta #else 2961f6ccfffSVineet Gupta unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15; 29756372082SVineet Gupta #endif 29856372082SVineet Gupta }; 29956372082SVineet Gupta 30056372082SVineet Gupta struct bcr_bpu_arcompact { 30156372082SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 30256372082SVineet Gupta unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8; 30356372082SVineet Gupta #else 30456372082SVineet Gupta unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19; 30556372082SVineet Gupta #endif 30656372082SVineet Gupta }; 30756372082SVineet Gupta 3081f6ccfffSVineet Gupta struct bcr_bpu_arcv2 { 3091f6ccfffSVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 3101f6ccfffSVineet Gupta unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8; 3111f6ccfffSVineet Gupta #else 3121f6ccfffSVineet Gupta unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6; 3131f6ccfffSVineet Gupta #endif 3141f6ccfffSVineet Gupta }; 3151f6ccfffSVineet Gupta 31656372082SVineet Gupta struct bcr_generic { 31756372082SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 318a150b085SVineet Gupta unsigned int info:24, ver:8; 31956372082SVineet Gupta #else 320a150b085SVineet Gupta unsigned int ver:8, info:24; 32156372082SVineet Gupta #endif 32256372082SVineet Gupta }; 32356372082SVineet Gupta 32495d6976dSVineet Gupta /* 32595d6976dSVineet Gupta ******************************************************************* 32695d6976dSVineet Gupta * Generic structures to hold build configuration used at runtime 32795d6976dSVineet Gupta */ 32895d6976dSVineet Gupta 329cc562d2eSVineet Gupta struct cpuinfo_arc_mmu { 330d0890ea5SVineet Gupta unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:10, sasid:1, pae:1; 331b598e17fSVineet Gupta unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8; 332cc562d2eSVineet Gupta }; 333cc562d2eSVineet Gupta 33495d6976dSVineet Gupta struct cpuinfo_arc_cache { 335d1f317d8SVineet Gupta unsigned int sz_k:14, line_len:8, assoc:4, ver:4, alias:1, vipt:1; 33695d6976dSVineet Gupta }; 33795d6976dSVineet Gupta 33856372082SVineet Gupta struct cpuinfo_arc_bpu { 33956372082SVineet Gupta unsigned int ver, full, num_cache, num_pred; 34056372082SVineet Gupta }; 34156372082SVineet Gupta 342af617428SVineet Gupta struct cpuinfo_arc_ccm { 343af617428SVineet Gupta unsigned int base_addr, sz; 344af617428SVineet Gupta }; 345af617428SVineet Gupta 34695d6976dSVineet Gupta struct cpuinfo_arc { 347d1f317d8SVineet Gupta struct cpuinfo_arc_cache icache, dcache, slc; 348cc562d2eSVineet Gupta struct cpuinfo_arc_mmu mmu; 34956372082SVineet Gupta struct cpuinfo_arc_bpu bpu; 350af617428SVineet Gupta struct bcr_identity core; 35156372082SVineet Gupta struct bcr_isa isa; 35273e284d2SVineet Gupta const char *details; 353af617428SVineet Gupta unsigned int vec_base; 354af617428SVineet Gupta struct cpuinfo_arc_ccm iccm, dccm; 35556372082SVineet Gupta struct { 356a024fd9bSVineet Gupta unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2, 35756372082SVineet Gupta fpu_sp:1, fpu_dp:1, pad2:6, 35856372082SVineet Gupta debug:1, ap:1, smart:1, rtt:1, pad3:4, 359b89bd1f4SVineet Gupta timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4; 36056372082SVineet Gupta } extn; 36156372082SVineet Gupta struct bcr_mpy extn_mpy; 362af617428SVineet Gupta struct bcr_extn_xymem extn_xymem; 36395d6976dSVineet Gupta }; 36495d6976dSVineet Gupta 36595d6976dSVineet Gupta extern struct cpuinfo_arc cpuinfo_arc700[]; 36695d6976dSVineet Gupta 3671f6ccfffSVineet Gupta static inline int is_isa_arcv2(void) 3681f6ccfffSVineet Gupta { 3691f6ccfffSVineet Gupta return IS_ENABLED(CONFIG_ISA_ARCV2); 3701f6ccfffSVineet Gupta } 3711f6ccfffSVineet Gupta 3721f6ccfffSVineet Gupta static inline int is_isa_arcompact(void) 3731f6ccfffSVineet Gupta { 3741f6ccfffSVineet Gupta return IS_ENABLED(CONFIG_ISA_ARCOMPACT); 3751f6ccfffSVineet Gupta } 3761f6ccfffSVineet Gupta 377ac4c244dSVineet Gupta #endif /* __ASEMBLY__ */ 378ac4c244dSVineet Gupta 379ac4c244dSVineet Gupta #endif /* _ASM_ARC_ARCREGS_H */ 380