1ac4c244dSVineet Gupta /* 2ac4c244dSVineet Gupta * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3ac4c244dSVineet Gupta * 4ac4c244dSVineet Gupta * This program is free software; you can redistribute it and/or modify 5ac4c244dSVineet Gupta * it under the terms of the GNU General Public License version 2 as 6ac4c244dSVineet Gupta * published by the Free Software Foundation. 7ac4c244dSVineet Gupta */ 8ac4c244dSVineet Gupta 9ac4c244dSVineet Gupta #ifndef _ASM_ARC_ARCREGS_H 10ac4c244dSVineet Gupta #define _ASM_ARC_ARCREGS_H 11ac4c244dSVineet Gupta 12ac4c244dSVineet Gupta #ifdef __KERNEL__ 13ac4c244dSVineet Gupta 14bacdf480SVineet Gupta /* Build Configuration Registers */ 15bacdf480SVineet Gupta #define ARC_REG_VECBASE_BCR 0x68 16bacdf480SVineet Gupta 17ac4c244dSVineet Gupta /* status32 Bits Positions */ 18ac4c244dSVineet Gupta #define STATUS_H_BIT 0 /* CPU Halted */ 19ac4c244dSVineet Gupta #define STATUS_E1_BIT 1 /* Int 1 enable */ 20ac4c244dSVineet Gupta #define STATUS_E2_BIT 2 /* Int 2 enable */ 21ac4c244dSVineet Gupta #define STATUS_A1_BIT 3 /* Int 1 active */ 22ac4c244dSVineet Gupta #define STATUS_A2_BIT 4 /* Int 2 active */ 23ac4c244dSVineet Gupta #define STATUS_AE_BIT 5 /* Exception active */ 24ac4c244dSVineet Gupta #define STATUS_DE_BIT 6 /* PC is in delay slot */ 25ac4c244dSVineet Gupta #define STATUS_U_BIT 7 /* User/Kernel mode */ 26ac4c244dSVineet Gupta #define STATUS_L_BIT 12 /* Loop inhibit */ 27ac4c244dSVineet Gupta 28ac4c244dSVineet Gupta /* These masks correspond to the status word(STATUS_32) bits */ 29ac4c244dSVineet Gupta #define STATUS_H_MASK (1<<STATUS_H_BIT) 30ac4c244dSVineet Gupta #define STATUS_E1_MASK (1<<STATUS_E1_BIT) 31ac4c244dSVineet Gupta #define STATUS_E2_MASK (1<<STATUS_E2_BIT) 32ac4c244dSVineet Gupta #define STATUS_A1_MASK (1<<STATUS_A1_BIT) 33ac4c244dSVineet Gupta #define STATUS_A2_MASK (1<<STATUS_A2_BIT) 34ac4c244dSVineet Gupta #define STATUS_AE_MASK (1<<STATUS_AE_BIT) 35ac4c244dSVineet Gupta #define STATUS_DE_MASK (1<<STATUS_DE_BIT) 36ac4c244dSVineet Gupta #define STATUS_U_MASK (1<<STATUS_U_BIT) 37ac4c244dSVineet Gupta #define STATUS_L_MASK (1<<STATUS_L_BIT) 38ac4c244dSVineet Gupta 39ac4c244dSVineet Gupta /* Auxiliary registers */ 40ac4c244dSVineet Gupta #define AUX_IDENTITY 4 41ac4c244dSVineet Gupta #define AUX_INTR_VEC_BASE 0x25 42ac4c244dSVineet Gupta #define AUX_IRQ_LEV 0x200 /* IRQ Priority: L1 or L2 */ 43ac4c244dSVineet Gupta #define AUX_IRQ_HINT 0x201 /* For generating Soft Interrupts */ 44ac4c244dSVineet Gupta #define AUX_IRQ_LV12 0x43 /* interrupt level register */ 45ac4c244dSVineet Gupta 46ac4c244dSVineet Gupta #define AUX_IENABLE 0x40c 47ac4c244dSVineet Gupta #define AUX_ITRIGGER 0x40d 48ac4c244dSVineet Gupta #define AUX_IPULSE 0x415 49ac4c244dSVineet Gupta 50d8005e6bSVineet Gupta /* Timer related Aux registers */ 51d8005e6bSVineet Gupta #define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */ 52d8005e6bSVineet Gupta #define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */ 53d8005e6bSVineet Gupta #define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */ 54d8005e6bSVineet Gupta #define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */ 55d8005e6bSVineet Gupta #define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */ 56d8005e6bSVineet Gupta #define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */ 57d8005e6bSVineet Gupta 58d8005e6bSVineet Gupta #define TIMER_CTRL_IE (1 << 0) /* Interupt when Count reachs limit */ 59d8005e6bSVineet Gupta #define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */ 60d8005e6bSVineet Gupta 6195d6976dSVineet Gupta /* Instruction cache related Auxiliary registers */ 6295d6976dSVineet Gupta #define ARC_REG_IC_BCR 0x77 /* Build Config reg */ 6395d6976dSVineet Gupta #define ARC_REG_IC_IVIC 0x10 6495d6976dSVineet Gupta #define ARC_REG_IC_CTRL 0x11 6595d6976dSVineet Gupta #define ARC_REG_IC_IVIL 0x19 6695d6976dSVineet Gupta #if (CONFIG_ARC_MMU_VER > 2) 6795d6976dSVineet Gupta #define ARC_REG_IC_PTAG 0x1E 6895d6976dSVineet Gupta #endif 6995d6976dSVineet Gupta 7095d6976dSVineet Gupta /* Bit val in IC_CTRL */ 7195d6976dSVineet Gupta #define IC_CTRL_CACHE_DISABLE 0x1 7295d6976dSVineet Gupta 7395d6976dSVineet Gupta /* Data cache related Auxiliary registers */ 7495d6976dSVineet Gupta #define ARC_REG_DC_BCR 0x72 7595d6976dSVineet Gupta #define ARC_REG_DC_IVDC 0x47 7695d6976dSVineet Gupta #define ARC_REG_DC_CTRL 0x48 7795d6976dSVineet Gupta #define ARC_REG_DC_IVDL 0x4A 7895d6976dSVineet Gupta #define ARC_REG_DC_FLSH 0x4B 7995d6976dSVineet Gupta #define ARC_REG_DC_FLDL 0x4C 8095d6976dSVineet Gupta #if (CONFIG_ARC_MMU_VER > 2) 8195d6976dSVineet Gupta #define ARC_REG_DC_PTAG 0x5C 8295d6976dSVineet Gupta #endif 8395d6976dSVineet Gupta 8495d6976dSVineet Gupta /* Bit val in DC_CTRL */ 8595d6976dSVineet Gupta #define DC_CTRL_INV_MODE_FLUSH 0x40 8695d6976dSVineet Gupta #define DC_CTRL_FLUSH_STATUS 0x100 8795d6976dSVineet Gupta 88bf90e1eaSVineet Gupta /* 89bf90e1eaSVineet Gupta * Floating Pt Registers 90bf90e1eaSVineet Gupta * Status regs are read-only (build-time) so need not be saved/restored 91bf90e1eaSVineet Gupta */ 92bf90e1eaSVineet Gupta #define ARC_AUX_FP_STAT 0x300 93bf90e1eaSVineet Gupta #define ARC_AUX_DPFP_1L 0x301 94bf90e1eaSVineet Gupta #define ARC_AUX_DPFP_1H 0x302 95bf90e1eaSVineet Gupta #define ARC_AUX_DPFP_2L 0x303 96bf90e1eaSVineet Gupta #define ARC_AUX_DPFP_2H 0x304 97bf90e1eaSVineet Gupta #define ARC_AUX_DPFP_STAT 0x305 98bf90e1eaSVineet Gupta 99ac4c244dSVineet Gupta #ifndef __ASSEMBLY__ 100ac4c244dSVineet Gupta 101ac4c244dSVineet Gupta /* 102ac4c244dSVineet Gupta ****************************************************************** 103ac4c244dSVineet Gupta * Inline ASM macros to read/write AUX Regs 104ac4c244dSVineet Gupta * Essentially invocation of lr/sr insns from "C" 105ac4c244dSVineet Gupta */ 106ac4c244dSVineet Gupta 107ac4c244dSVineet Gupta #if 1 108ac4c244dSVineet Gupta 109ac4c244dSVineet Gupta #define read_aux_reg(reg) __builtin_arc_lr(reg) 110ac4c244dSVineet Gupta 111ac4c244dSVineet Gupta /* gcc builtin sr needs reg param to be long immediate */ 112ac4c244dSVineet Gupta #define write_aux_reg(reg_immed, val) \ 113ac4c244dSVineet Gupta __builtin_arc_sr((unsigned int)val, reg_immed) 114ac4c244dSVineet Gupta 115ac4c244dSVineet Gupta #else 116ac4c244dSVineet Gupta 117ac4c244dSVineet Gupta #define read_aux_reg(reg) \ 118ac4c244dSVineet Gupta ({ \ 119ac4c244dSVineet Gupta unsigned int __ret; \ 120ac4c244dSVineet Gupta __asm__ __volatile__( \ 121ac4c244dSVineet Gupta " lr %0, [%1]" \ 122ac4c244dSVineet Gupta : "=r"(__ret) \ 123ac4c244dSVineet Gupta : "i"(reg)); \ 124ac4c244dSVineet Gupta __ret; \ 125ac4c244dSVineet Gupta }) 126ac4c244dSVineet Gupta 127ac4c244dSVineet Gupta /* 128ac4c244dSVineet Gupta * Aux Reg address is specified as long immediate by caller 129ac4c244dSVineet Gupta * e.g. 130ac4c244dSVineet Gupta * write_aux_reg(0x69, some_val); 131ac4c244dSVineet Gupta * This generates tightest code. 132ac4c244dSVineet Gupta */ 133ac4c244dSVineet Gupta #define write_aux_reg(reg_imm, val) \ 134ac4c244dSVineet Gupta ({ \ 135ac4c244dSVineet Gupta __asm__ __volatile__( \ 136ac4c244dSVineet Gupta " sr %0, [%1] \n" \ 137ac4c244dSVineet Gupta : \ 138ac4c244dSVineet Gupta : "ir"(val), "i"(reg_imm)); \ 139ac4c244dSVineet Gupta }) 140ac4c244dSVineet Gupta 141ac4c244dSVineet Gupta /* 142ac4c244dSVineet Gupta * Aux Reg address is specified in a variable 143ac4c244dSVineet Gupta * * e.g. 144ac4c244dSVineet Gupta * reg_num = 0x69 145ac4c244dSVineet Gupta * write_aux_reg2(reg_num, some_val); 146ac4c244dSVineet Gupta * This has to generate glue code to load the reg num from 147ac4c244dSVineet Gupta * memory to a reg hence not recommended. 148ac4c244dSVineet Gupta */ 149ac4c244dSVineet Gupta #define write_aux_reg2(reg_in_var, val) \ 150ac4c244dSVineet Gupta ({ \ 151ac4c244dSVineet Gupta unsigned int tmp; \ 152ac4c244dSVineet Gupta \ 153ac4c244dSVineet Gupta __asm__ __volatile__( \ 154ac4c244dSVineet Gupta " ld %0, [%2] \n\t" \ 155ac4c244dSVineet Gupta " sr %1, [%0] \n\t" \ 156ac4c244dSVineet Gupta : "=&r"(tmp) \ 157ac4c244dSVineet Gupta : "r"(val), "memory"(®_in_var)); \ 158ac4c244dSVineet Gupta }) 159ac4c244dSVineet Gupta 160ac4c244dSVineet Gupta #endif 161ac4c244dSVineet Gupta 16295d6976dSVineet Gupta #define READ_BCR(reg, into) \ 16395d6976dSVineet Gupta { \ 16495d6976dSVineet Gupta unsigned int tmp; \ 16595d6976dSVineet Gupta tmp = read_aux_reg(reg); \ 16695d6976dSVineet Gupta if (sizeof(tmp) == sizeof(into)) { \ 16795d6976dSVineet Gupta into = *((typeof(into) *)&tmp); \ 16895d6976dSVineet Gupta } else { \ 16995d6976dSVineet Gupta extern void bogus_undefined(void); \ 17095d6976dSVineet Gupta bogus_undefined(); \ 17195d6976dSVineet Gupta } \ 17295d6976dSVineet Gupta } 17395d6976dSVineet Gupta 17495d6976dSVineet Gupta #define WRITE_BCR(reg, into) \ 17595d6976dSVineet Gupta { \ 17695d6976dSVineet Gupta unsigned int tmp; \ 17795d6976dSVineet Gupta if (sizeof(tmp) == sizeof(into)) { \ 17895d6976dSVineet Gupta tmp = (*(unsigned int *)(into)); \ 17995d6976dSVineet Gupta write_aux_reg(reg, tmp); \ 18095d6976dSVineet Gupta } else { \ 18195d6976dSVineet Gupta extern void bogus_undefined(void); \ 18295d6976dSVineet Gupta bogus_undefined(); \ 18395d6976dSVineet Gupta } \ 18495d6976dSVineet Gupta } 18595d6976dSVineet Gupta 18695d6976dSVineet Gupta 187bf90e1eaSVineet Gupta #ifdef CONFIG_ARC_FPU_SAVE_RESTORE 188bf90e1eaSVineet Gupta /* These DPFP regs need to be saved/restored across ctx-sw */ 189bf90e1eaSVineet Gupta struct arc_fpu { 190bf90e1eaSVineet Gupta struct { 191bf90e1eaSVineet Gupta unsigned int l, h; 192bf90e1eaSVineet Gupta } aux_dpfp[2]; 193bf90e1eaSVineet Gupta }; 194bf90e1eaSVineet Gupta #endif 195bf90e1eaSVineet Gupta 19695d6976dSVineet Gupta /* 19795d6976dSVineet Gupta *************************************************************** 19895d6976dSVineet Gupta * Build Configuration Registers, with encoded hardware config 19995d6976dSVineet Gupta */ 20095d6976dSVineet Gupta 20195d6976dSVineet Gupta struct bcr_cache { 20295d6976dSVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 20395d6976dSVineet Gupta unsigned int pad:12, line_len:4, sz:4, config:4, ver:8; 20495d6976dSVineet Gupta #else 20595d6976dSVineet Gupta unsigned int ver:8, config:4, sz:4, line_len:4, pad:12; 20695d6976dSVineet Gupta #endif 20795d6976dSVineet Gupta }; 20895d6976dSVineet Gupta 20995d6976dSVineet Gupta /* 21095d6976dSVineet Gupta ******************************************************************* 21195d6976dSVineet Gupta * Generic structures to hold build configuration used at runtime 21295d6976dSVineet Gupta */ 21395d6976dSVineet Gupta 21495d6976dSVineet Gupta struct cpuinfo_arc_cache { 21595d6976dSVineet Gupta unsigned int has_aliasing, sz, line_len, assoc, ver; 21695d6976dSVineet Gupta }; 21795d6976dSVineet Gupta 21895d6976dSVineet Gupta struct cpuinfo_arc { 21995d6976dSVineet Gupta struct cpuinfo_arc_cache icache, dcache; 22095d6976dSVineet Gupta }; 22195d6976dSVineet Gupta 22295d6976dSVineet Gupta extern struct cpuinfo_arc cpuinfo_arc700[]; 22395d6976dSVineet Gupta 224ac4c244dSVineet Gupta #endif /* __ASEMBLY__ */ 225ac4c244dSVineet Gupta 226ac4c244dSVineet Gupta #endif /* __KERNEL__ */ 227ac4c244dSVineet Gupta 228ac4c244dSVineet Gupta #endif /* _ASM_ARC_ARCREGS_H */ 229