1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2ac4c244dSVineet Gupta /* 3ac4c244dSVineet Gupta * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 4ac4c244dSVineet Gupta */ 5ac4c244dSVineet Gupta 6ac4c244dSVineet Gupta #ifndef _ASM_ARC_ARCREGS_H 7ac4c244dSVineet Gupta #define _ASM_ARC_ARCREGS_H 8ac4c244dSVineet Gupta 9bacdf480SVineet Gupta /* Build Configuration Registers */ 10a150b085SVineet Gupta #define ARC_REG_AUX_DCCM 0x18 /* DCCM Base Addr ARCv2 */ 11f3156851SVineet Gupta #define ARC_REG_ERP_CTRL 0x3F /* ARCv2 Error protection control */ 12a150b085SVineet Gupta #define ARC_REG_DCCM_BASE_BUILD 0x61 /* DCCM Base Addr ARCompact */ 13af617428SVineet Gupta #define ARC_REG_CRC_BCR 0x62 14bacdf480SVineet Gupta #define ARC_REG_VECBASE_BCR 0x68 15af617428SVineet Gupta #define ARC_REG_PERIBASE_BCR 0x69 1656372082SVineet Gupta #define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */ 1756372082SVineet Gupta #define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */ 18f3156851SVineet Gupta #define ARC_REG_ERP_BUILD 0xc7 /* ARCv2 Error protection Build: ECC/Parity */ 191f6ccfffSVineet Gupta #define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */ 20d1f317d8SVineet Gupta #define ARC_REG_SLC_BCR 0xce 21a150b085SVineet Gupta #define ARC_REG_DCCM_BUILD 0x74 /* DCCM size (common) */ 2256372082SVineet Gupta #define ARC_REG_AP_BCR 0x76 23a150b085SVineet Gupta #define ARC_REG_ICCM_BUILD 0x78 /* ICCM size (common) */ 24af617428SVineet Gupta #define ARC_REG_XY_MEM_BCR 0x79 25af617428SVineet Gupta #define ARC_REG_MAC_BCR 0x7a 26af617428SVineet Gupta #define ARC_REG_MUL_BCR 0x7b 27af617428SVineet Gupta #define ARC_REG_SWAP_BCR 0x7c 28af617428SVineet Gupta #define ARC_REG_NORM_BCR 0x7d 29af617428SVineet Gupta #define ARC_REG_MIXMAX_BCR 0x7e 30af617428SVineet Gupta #define ARC_REG_BARREL_BCR 0x7f 31af617428SVineet Gupta #define ARC_REG_D_UNCACH_BCR 0x6A 3256372082SVineet Gupta #define ARC_REG_BPU_BCR 0xc0 3356372082SVineet Gupta #define ARC_REG_ISA_CFG_BCR 0xc1 34f3156851SVineet Gupta #define ARC_REG_LPB_BUILD 0xE9 /* ARCv2 Loop Buffer Build */ 35a44ec8bdSVineet Gupta #define ARC_REG_RTT_BCR 0xF2 36820970a5SVineet Gupta #define ARC_REG_IRQ_BCR 0xF3 37f3156851SVineet Gupta #define ARC_REG_MICRO_ARCH_BCR 0xF9 /* ARCv2 Product revision */ 3856372082SVineet Gupta #define ARC_REG_SMART_BCR 0xFF 39f2b0b25aSAlexey Brodkin #define ARC_REG_CLUSTER_BCR 0xcf 40a150b085SVineet Gupta #define ARC_REG_AUX_ICCM 0x208 /* ICCM Base Addr (ARCv2) */ 41f3156851SVineet Gupta #define ARC_REG_LPB_CTRL 0x488 /* ARCv2 Loop Buffer control */ 42f45ba2bdSVineet Gupta #define ARC_REG_FPU_CTRL 0x300 43f45ba2bdSVineet Gupta #define ARC_REG_FPU_STATUS 0x301 44bacdf480SVineet Gupta 45e98a7bf0SYuriy Kolerov /* Common for ARCompact and ARCv2 status register */ 46e98a7bf0SYuriy Kolerov #define ARC_REG_STATUS32 0x0A 47e98a7bf0SYuriy Kolerov 48ac4c244dSVineet Gupta /* status32 Bits Positions */ 49ac4c244dSVineet Gupta #define STATUS_AE_BIT 5 /* Exception active */ 50ac4c244dSVineet Gupta #define STATUS_DE_BIT 6 /* PC is in delay slot */ 51ac4c244dSVineet Gupta #define STATUS_U_BIT 7 /* User/Kernel mode */ 52e6e335bfSVineet Gupta #define STATUS_Z_BIT 11 53ac4c244dSVineet Gupta #define STATUS_L_BIT 12 /* Loop inhibit */ 54ac4c244dSVineet Gupta 55ac4c244dSVineet Gupta /* These masks correspond to the status word(STATUS_32) bits */ 56ac4c244dSVineet Gupta #define STATUS_AE_MASK (1<<STATUS_AE_BIT) 57ac4c244dSVineet Gupta #define STATUS_DE_MASK (1<<STATUS_DE_BIT) 58ac4c244dSVineet Gupta #define STATUS_U_MASK (1<<STATUS_U_BIT) 59e6e335bfSVineet Gupta #define STATUS_Z_MASK (1<<STATUS_Z_BIT) 60ac4c244dSVineet Gupta #define STATUS_L_MASK (1<<STATUS_L_BIT) 61ac4c244dSVineet Gupta 62cc562d2eSVineet Gupta /* 63cc562d2eSVineet Gupta * ECR: Exception Cause Reg bits-n-pieces 64cc562d2eSVineet Gupta * [23:16] = Exception Vector 65cc562d2eSVineet Gupta * [15: 8] = Exception Cause Code 66cc562d2eSVineet Gupta * [ 7: 0] = Exception Parameters (for certain types only) 67cc562d2eSVineet Gupta */ 681f6ccfffSVineet Gupta #ifdef CONFIG_ISA_ARCOMPACT 69dc9e234fSVineet Gupta #define ECR_V_MEM_ERR 0x01 70cc562d2eSVineet Gupta #define ECR_V_INSN_ERR 0x02 71cc562d2eSVineet Gupta #define ECR_V_MACH_CHK 0x20 72cc562d2eSVineet Gupta #define ECR_V_ITLB_MISS 0x21 73cc562d2eSVineet Gupta #define ECR_V_DTLB_MISS 0x22 74cc562d2eSVineet Gupta #define ECR_V_PROTV 0x23 75502a0c77SVineet Gupta #define ECR_V_TRAP 0x25 761f6ccfffSVineet Gupta #else 771f6ccfffSVineet Gupta #define ECR_V_MEM_ERR 0x01 781f6ccfffSVineet Gupta #define ECR_V_INSN_ERR 0x02 791f6ccfffSVineet Gupta #define ECR_V_MACH_CHK 0x03 801f6ccfffSVineet Gupta #define ECR_V_ITLB_MISS 0x04 811f6ccfffSVineet Gupta #define ECR_V_DTLB_MISS 0x05 821f6ccfffSVineet Gupta #define ECR_V_PROTV 0x06 831f6ccfffSVineet Gupta #define ECR_V_TRAP 0x09 8476551468SEugeniy Paltsev #define ECR_V_MISALIGN 0x0d 851f6ccfffSVineet Gupta #endif 86cc562d2eSVineet Gupta 87dc9e234fSVineet Gupta /* DTLB Miss and Protection Violation Cause Codes */ 88dc9e234fSVineet Gupta 89cc562d2eSVineet Gupta #define ECR_C_PROTV_INST_FETCH 0x00 90cc562d2eSVineet Gupta #define ECR_C_PROTV_LOAD 0x01 91cc562d2eSVineet Gupta #define ECR_C_PROTV_STORE 0x02 92cc562d2eSVineet Gupta #define ECR_C_PROTV_XCHG 0x03 93cc562d2eSVineet Gupta #define ECR_C_PROTV_MISALIG_DATA 0x04 94cc562d2eSVineet Gupta 951898a959SVineet Gupta #define ECR_C_BIT_PROTV_MISALIG_DATA 10 961898a959SVineet Gupta 971898a959SVineet Gupta /* Machine Check Cause Code Values */ 981898a959SVineet Gupta #define ECR_C_MCHK_DUP_TLB 0x01 991898a959SVineet Gupta 100cc562d2eSVineet Gupta /* DTLB Miss Exception Cause Code Values */ 101cc562d2eSVineet Gupta #define ECR_C_BIT_DTLB_LD_MISS 8 102cc562d2eSVineet Gupta #define ECR_C_BIT_DTLB_ST_MISS 9 103cc562d2eSVineet Gupta 104ac4c244dSVineet Gupta /* Auxiliary registers */ 105ac4c244dSVineet Gupta #define AUX_IDENTITY 4 106dea82520SVineet Gupta #define AUX_EXEC_CTRL 8 107ac4c244dSVineet Gupta #define AUX_INTR_VEC_BASE 0x25 10826c01c49SVineet Gupta #define AUX_VOL 0x5e 109f1f3347dSVineet Gupta 110bf90e1eaSVineet Gupta /* 111bf90e1eaSVineet Gupta * Floating Pt Registers 112bf90e1eaSVineet Gupta * Status regs are read-only (build-time) so need not be saved/restored 113bf90e1eaSVineet Gupta */ 114bf90e1eaSVineet Gupta #define ARC_AUX_FP_STAT 0x300 115bf90e1eaSVineet Gupta #define ARC_AUX_DPFP_1L 0x301 116bf90e1eaSVineet Gupta #define ARC_AUX_DPFP_1H 0x302 117bf90e1eaSVineet Gupta #define ARC_AUX_DPFP_2L 0x303 118bf90e1eaSVineet Gupta #define ARC_AUX_DPFP_2H 0x304 119bf90e1eaSVineet Gupta #define ARC_AUX_DPFP_STAT 0x305 120bf90e1eaSVineet Gupta 1214827d0cfSEugeniy Paltsev /* 1224827d0cfSEugeniy Paltsev * DSP-related registers 1237321e2eaSEugeniy Paltsev * Registers names must correspond to dsp_callee_regs structure fields names 1247321e2eaSEugeniy Paltsev * for automatic offset calculation in DSP_AUX_SAVE_RESTORE macros. 1254827d0cfSEugeniy Paltsev */ 1264827d0cfSEugeniy Paltsev #define ARC_AUX_DSP_BUILD 0x7A 1274827d0cfSEugeniy Paltsev #define ARC_AUX_ACC0_LO 0x580 1284827d0cfSEugeniy Paltsev #define ARC_AUX_ACC0_GLO 0x581 1294827d0cfSEugeniy Paltsev #define ARC_AUX_ACC0_HI 0x582 1304827d0cfSEugeniy Paltsev #define ARC_AUX_ACC0_GHI 0x583 1314827d0cfSEugeniy Paltsev #define ARC_AUX_DSP_BFLY0 0x598 1324827d0cfSEugeniy Paltsev #define ARC_AUX_DSP_CTRL 0x59F 1334827d0cfSEugeniy Paltsev #define ARC_AUX_DSP_FFT_CTRL 0x59E 1344827d0cfSEugeniy Paltsev 135ac4c244dSVineet Gupta #ifndef __ASSEMBLY__ 136ac4c244dSVineet Gupta 137c33a605dSVineet Gupta #include <soc/arc/aux.h> 13895d6976dSVineet Gupta 139c121c506SVineet Gupta /* Helpers */ 140c121c506SVineet Gupta #define TO_KB(bytes) ((bytes) >> 10) 141c121c506SVineet Gupta #define TO_MB(bytes) (TO_KB(bytes) >> 10) 142c121c506SVineet Gupta #define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10)) 143c121c506SVineet Gupta #define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10) 14495d6976dSVineet Gupta 145bf90e1eaSVineet Gupta 14695d6976dSVineet Gupta /* 14795d6976dSVineet Gupta *************************************************************** 14895d6976dSVineet Gupta * Build Configuration Registers, with encoded hardware config 14995d6976dSVineet Gupta */ 150af617428SVineet Gupta struct bcr_identity { 151af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 152af617428SVineet Gupta unsigned int chip_id:16, cpu_id:8, family:8; 153af617428SVineet Gupta #else 154af617428SVineet Gupta unsigned int family:8, cpu_id:8, chip_id:16; 155af617428SVineet Gupta #endif 156af617428SVineet Gupta }; 15795d6976dSVineet Gupta 158010a8c98SVineet Gupta struct bcr_isa_arcv2 { 159af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 1601f6ccfffSVineet Gupta unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1, 161010a8c98SVineet Gupta pad1:12, ver:8; 162af617428SVineet Gupta #else 163010a8c98SVineet Gupta unsigned int ver:8, pad1:12, be:1, atomic:1, unalign:1, 1641f6ccfffSVineet Gupta ldd:1, pad2:4, div_rem:4; 165af617428SVineet Gupta #endif 166af617428SVineet Gupta }; 167af617428SVineet Gupta 1687b2e932fSVineet Gupta struct bcr_uarch_build_arcv2 { 1697b2e932fSVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 1707b2e932fSVineet Gupta unsigned int pad:8, prod:8, maj:8, min:8; 1717b2e932fSVineet Gupta #else 1727b2e932fSVineet Gupta unsigned int min:8, maj:8, prod:8, pad:8; 1737b2e932fSVineet Gupta #endif 1747b2e932fSVineet Gupta }; 1757b2e932fSVineet Gupta 17656372082SVineet Gupta struct bcr_mpy { 177af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 17856372082SVineet Gupta unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8; 179af617428SVineet Gupta #else 18056372082SVineet Gupta unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8; 181af617428SVineet Gupta #endif 182af617428SVineet Gupta }; 183af617428SVineet Gupta 184a150b085SVineet Gupta struct bcr_iccm_arcompact { 185af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 186af617428SVineet Gupta unsigned int base:16, pad:5, sz:3, ver:8; 187af617428SVineet Gupta #else 188af617428SVineet Gupta unsigned int ver:8, sz:3, pad:5, base:16; 189af617428SVineet Gupta #endif 190af617428SVineet Gupta }; 191af617428SVineet Gupta 192a150b085SVineet Gupta struct bcr_iccm_arcv2 { 193af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 194a150b085SVineet Gupta unsigned int pad:8, sz11:4, sz01:4, sz10:4, sz00:4, ver:8; 195af617428SVineet Gupta #else 196a150b085SVineet Gupta unsigned int ver:8, sz00:4, sz10:4, sz01:4, sz11:4, pad:8; 197af617428SVineet Gupta #endif 198af617428SVineet Gupta }; 199af617428SVineet Gupta 200a150b085SVineet Gupta struct bcr_dccm_arcompact { 201af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 202af617428SVineet Gupta unsigned int res:21, sz:3, ver:8; 203af617428SVineet Gupta #else 204af617428SVineet Gupta unsigned int ver:8, sz:3, res:21; 205af617428SVineet Gupta #endif 206af617428SVineet Gupta }; 207af617428SVineet Gupta 208a150b085SVineet Gupta struct bcr_dccm_arcv2 { 209a150b085SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 210a150b085SVineet Gupta unsigned int pad2:12, cyc:3, pad1:1, sz1:4, sz0:4, ver:8; 211a150b085SVineet Gupta #else 212a150b085SVineet Gupta unsigned int ver:8, sz0:4, sz1:4, pad1:1, cyc:3, pad2:12; 213a150b085SVineet Gupta #endif 214a150b085SVineet Gupta }; 215a150b085SVineet Gupta 21656372082SVineet Gupta /* ARCompact: Both SP and DP FPU BCRs have same format */ 21756372082SVineet Gupta struct bcr_fp_arcompact { 218af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 219af617428SVineet Gupta unsigned int fast:1, ver:8; 220af617428SVineet Gupta #else 221af617428SVineet Gupta unsigned int ver:8, fast:1; 222af617428SVineet Gupta #endif 223af617428SVineet Gupta }; 224af617428SVineet Gupta 2251f6ccfffSVineet Gupta struct bcr_fp_arcv2 { 2261f6ccfffSVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 2271f6ccfffSVineet Gupta unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8; 2281f6ccfffSVineet Gupta #else 2291f6ccfffSVineet Gupta unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15; 2301f6ccfffSVineet Gupta #endif 2311f6ccfffSVineet Gupta }; 2321f6ccfffSVineet Gupta 2337dd380c3SVineet Gupta struct bcr_actionpoint { 2347dd380c3SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 2357dd380c3SVineet Gupta unsigned int pad:21, min:1, num:2, ver:8; 2367dd380c3SVineet Gupta #else 2377dd380c3SVineet Gupta unsigned int ver:8, num:2, min:1, pad:21; 2387dd380c3SVineet Gupta #endif 2397dd380c3SVineet Gupta }; 2407dd380c3SVineet Gupta 241b26c2e38SVineet Gupta #include <soc/arc/timers.h> 24256372082SVineet Gupta 24356372082SVineet Gupta struct bcr_bpu_arcompact { 24456372082SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 24556372082SVineet Gupta unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8; 24656372082SVineet Gupta #else 24756372082SVineet Gupta unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19; 24856372082SVineet Gupta #endif 24956372082SVineet Gupta }; 25056372082SVineet Gupta 2511f6ccfffSVineet Gupta struct bcr_bpu_arcv2 { 2521f6ccfffSVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 2531f6ccfffSVineet Gupta unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8; 2541f6ccfffSVineet Gupta #else 2551f6ccfffSVineet Gupta unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6; 2561f6ccfffSVineet Gupta #endif 2571f6ccfffSVineet Gupta }; 2581f6ccfffSVineet Gupta 259f3156851SVineet Gupta /* Error Protection Build: ECC/Parity */ 260f3156851SVineet Gupta struct bcr_erp { 261f3156851SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 262f3156851SVineet Gupta unsigned int pad3:5, mmu:3, pad2:4, ic:3, dc:3, pad1:6, ver:8; 263f3156851SVineet Gupta #else 264f3156851SVineet Gupta unsigned int ver:8, pad1:6, dc:3, ic:3, pad2:4, mmu:3, pad3:5; 265f3156851SVineet Gupta #endif 266f3156851SVineet Gupta }; 267f3156851SVineet Gupta 268f3156851SVineet Gupta /* Error Protection Control */ 269f3156851SVineet Gupta struct ctl_erp { 270f3156851SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 271f3156851SVineet Gupta unsigned int pad2:27, mpd:1, pad1:2, dpd:1, dpi:1; 272f3156851SVineet Gupta #else 273f3156851SVineet Gupta unsigned int dpi:1, dpd:1, pad1:2, mpd:1, pad2:27; 274f3156851SVineet Gupta #endif 275f3156851SVineet Gupta }; 276f3156851SVineet Gupta 277f3156851SVineet Gupta struct bcr_lpb { 278f3156851SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 279f3156851SVineet Gupta unsigned int pad:16, entries:8, ver:8; 280f3156851SVineet Gupta #else 281f3156851SVineet Gupta unsigned int ver:8, entries:8, pad:16; 282f3156851SVineet Gupta #endif 283f3156851SVineet Gupta }; 284f3156851SVineet Gupta 28556372082SVineet Gupta struct bcr_generic { 28656372082SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 287a150b085SVineet Gupta unsigned int info:24, ver:8; 28856372082SVineet Gupta #else 289a150b085SVineet Gupta unsigned int ver:8, info:24; 29056372082SVineet Gupta #endif 29156372082SVineet Gupta }; 29256372082SVineet Gupta 29395d6976dSVineet Gupta /* 29495d6976dSVineet Gupta ******************************************************************* 29595d6976dSVineet Gupta * Generic structures to hold build configuration used at runtime 29695d6976dSVineet Gupta */ 29795d6976dSVineet Gupta 298cc562d2eSVineet Gupta struct cpuinfo_arc_mmu { 299d0890ea5SVineet Gupta unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:10, sasid:1, pae:1; 300b598e17fSVineet Gupta unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8; 301cc562d2eSVineet Gupta }; 302cc562d2eSVineet Gupta 30395d6976dSVineet Gupta struct cpuinfo_arc_cache { 304f64915beSVineet Gupta unsigned int sz_k:14, line_len:8, assoc:4, alias:1, vipt:1, pad:4; 30595d6976dSVineet Gupta }; 30695d6976dSVineet Gupta 30756372082SVineet Gupta struct cpuinfo_arc_bpu { 30897e98132SVineet Gupta unsigned int ver, full, num_cache, num_pred, ret_stk; 30956372082SVineet Gupta }; 31056372082SVineet Gupta 311af617428SVineet Gupta struct cpuinfo_arc_ccm { 312af617428SVineet Gupta unsigned int base_addr, sz; 313af617428SVineet Gupta }; 314af617428SVineet Gupta 31595d6976dSVineet Gupta struct cpuinfo_arc { 316d1f317d8SVineet Gupta struct cpuinfo_arc_cache icache, dcache, slc; 317cc562d2eSVineet Gupta struct cpuinfo_arc_mmu mmu; 31856372082SVineet Gupta struct cpuinfo_arc_bpu bpu; 319af617428SVineet Gupta struct bcr_identity core; 320010a8c98SVineet Gupta struct bcr_isa_arcv2 isa; 32100a4ae65SVineet Gupta const char *release, *name; 322af617428SVineet Gupta unsigned int vec_base; 323af617428SVineet Gupta struct cpuinfo_arc_ccm iccm, dccm; 32456372082SVineet Gupta struct { 325a024fd9bSVineet Gupta unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2, 326f3156851SVineet Gupta fpu_sp:1, fpu_dp:1, dual:1, dual_enb:1, pad2:4, 3277dd380c3SVineet Gupta ap_num:4, ap_full:1, smart:1, rtt:1, pad3:1, 328b89bd1f4SVineet Gupta timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4; 32956372082SVineet Gupta } extn; 33056372082SVineet Gupta struct bcr_mpy extn_mpy; 33195d6976dSVineet Gupta }; 33295d6976dSVineet Gupta 33395d6976dSVineet Gupta extern struct cpuinfo_arc cpuinfo_arc700[]; 33495d6976dSVineet Gupta 3351f6ccfffSVineet Gupta static inline int is_isa_arcv2(void) 3361f6ccfffSVineet Gupta { 3371f6ccfffSVineet Gupta return IS_ENABLED(CONFIG_ISA_ARCV2); 3381f6ccfffSVineet Gupta } 3391f6ccfffSVineet Gupta 3401f6ccfffSVineet Gupta static inline int is_isa_arcompact(void) 3411f6ccfffSVineet Gupta { 3421f6ccfffSVineet Gupta return IS_ENABLED(CONFIG_ISA_ARCOMPACT); 3431f6ccfffSVineet Gupta } 3441f6ccfffSVineet Gupta 345ac4c244dSVineet Gupta #endif /* __ASEMBLY__ */ 346ac4c244dSVineet Gupta 347ac4c244dSVineet Gupta #endif /* _ASM_ARC_ARCREGS_H */ 348