1/*
2 * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Device tree for AXC003 CPU card:
11 * HS38x2 (Dual Core) with IDU intc (VDK version)
12 */
13
14/include/ "skeleton_hs_idu.dtsi"
15
16/ {
17	compatible = "snps,arc";
18	#address-cells = <1>;
19	#size-cells = <1>;
20
21	cpu_card {
22		compatible = "simple-bus";
23		#address-cells = <1>;
24		#size-cells = <1>;
25
26		ranges = <0x00000000 0xf0000000 0x10000000>;
27
28		core_clk: core_clk {
29			#clock-cells = <0>;
30			compatible = "fixed-clock";
31			clock-frequency = <50000000>;
32		};
33
34		core_intc: archs-intc@cpu {
35			compatible = "snps,archs-intc";
36			interrupt-controller;
37			#interrupt-cells = <1>;
38		};
39
40		idu_intc: idu-interrupt-controller {
41			compatible = "snps,archs-idu-intc";
42			interrupt-controller;
43			interrupt-parent = <&core_intc>;
44
45			/*
46			 * <hwirq  distribution>
47			 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
48			 */
49			#interrupt-cells = <2>;
50
51			interrupts = <24 25 26 27>;
52		};
53
54		debug_uart: dw-apb-uart@0x5000 {
55			compatible = "snps,dw-apb-uart";
56			reg = <0x5000 0x100>;
57			clock-frequency = <2403200>;
58			interrupt-parent = <&idu_intc>;
59			interrupts = <2 0>;
60			baud = <115200>;
61			reg-shift = <2>;
62			reg-io-width = <4>;
63		};
64
65	};
66
67	mb_intc: dw-apb-ictl@0xe0012000 {
68		#interrupt-cells = <1>;
69		compatible = "snps,dw-apb-ictl";
70		reg = < 0xe0012000 0x200 >;
71		interrupt-controller;
72		interrupt-parent = <&idu_intc>;
73		interrupts = < 0 0 >;
74	};
75
76	memory {
77		#address-cells = <1>;
78		#size-cells = <1>;
79		ranges = <0x00000000 0x80000000 0x40000000>;
80		device_type = "memory";
81		reg = <0x80000000 0x20000000>;	/* 512MiB */
82	};
83};
84