1/*
2 * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/ {
10	compatible = "snps,arc";
11	#address-cells = <1>;
12	#size-cells = <1>;
13	chosen { };
14	aliases { };
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		cpu@0 {
21			device_type = "cpu";
22			compatible = "snps,archs38";
23			reg = <0>;
24			clocks = <&core_clk>;
25		};
26		cpu@1 {
27			device_type = "cpu";
28			compatible = "snps,archs38";
29			reg = <1>;
30			clocks = <&core_clk>;
31		};
32		cpu@2 {
33			device_type = "cpu";
34			compatible = "snps,archs38";
35			reg = <2>;
36			clocks = <&core_clk>;
37		};
38		cpu@3 {
39			device_type = "cpu";
40			compatible = "snps,archs38";
41			reg = <3>;
42			clocks = <&core_clk>;
43		};
44	};
45
46	/* TIMER0 with interrupt for clockevent */
47	timer0 {
48		compatible = "snps,arc-timer";
49		interrupts = <16>;
50		interrupt-parent = <&core_intc>;
51		clocks = <&core_clk>;
52	};
53
54	/* 64-bit Global Free Running Counter */
55	gfrc {
56		compatible = "snps,archs-timer-gfrc";
57		clocks = <&core_clk>;
58	};
59
60	memory {
61		device_type = "memory";
62		reg = <0x80000000 0x10000000>;	/* 256M */
63	};
64};
65