1/*
2 * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/ {
10	compatible = "snps,arc";
11	clock-frequency = <80000000>;	/* 80 MHZ */
12	#address-cells = <1>;
13	#size-cells = <1>;
14	chosen { };
15	aliases { };
16
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20
21		cpu@0 {
22			device_type = "cpu";
23			compatible = "snps,archs38xN";
24			reg = <0>;
25		};
26	};
27
28	/* TIMER0 with interrupt for clockevent */
29	timer0 {
30		compatible = "snps,arc-timer";
31		interrupts = <16>;
32		interrupt-parent = <&core_intc>;
33		clocks = <&core_clk>;
34	};
35
36	/* 64-bit Global Free Running Counter */
37	gfrc {
38		compatible = "snps,archs-timer-gfrc";
39		clocks = <&core_clk>;
40	};
41
42	memory {
43		device_type = "memory";
44		reg = <0x80000000 0x10000000>;	/* 256M */
45	};
46};
47