1/*
2 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "skeleton_hs_idu.dtsi"
11
12/ {
13	compatible = "snps,nsimosci_hs";
14	#address-cells = <1>;
15	#size-cells = <1>;
16	interrupt-parent = <&core_intc>;
17
18	chosen {
19		/* this is for console on serial */
20		bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblan=0 debug video=640x480-24";
21	};
22
23	aliases {
24		serial0 = &uart0;
25	};
26
27	fpga {
28		compatible = "simple-bus";
29		#address-cells = <1>;
30		#size-cells = <1>;
31
32		/* child and parent address space 1:1 mapped */
33		ranges;
34
35		core_clk: core_clk {
36			#clock-cells = <0>;
37			compatible = "fixed-clock";
38			clock-frequency = <5000000>;
39		};
40
41		core_intc: core-interrupt-controller {
42			compatible = "snps,archs-intc";
43			interrupt-controller;
44			#interrupt-cells = <1>;
45/*			interrupts = <16 17 18 19 20 21 22 23 24 25>; */
46		};
47
48		idu_intc: idu-interrupt-controller {
49			compatible = "snps,archs-idu-intc";
50			interrupt-controller;
51			interrupt-parent = <&core_intc>;
52
53			/*
54			 * <hwirq  distribution>
55			 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
56			 */
57			#interrupt-cells = <2>;
58
59			/*
60			 * upstream irqs to core intc - downstream these are
61			 * "COMMON" irq 0,1..
62			 */
63			interrupts = <24 25 26 27 28 29 30 31>;
64		};
65
66		uart0: serial@f0000000 {
67			compatible = "ns8250";
68			reg = <0xf0000000 0x2000>;
69			interrupt-parent = <&idu_intc>;
70			interrupts = <0 0>; /* cmn irq 0 -> cpu irq 24
71						RR distribute to all cpus */
72			clock-frequency = <3686400>;
73			baud = <115200>;
74			reg-shift = <2>;
75			reg-io-width = <4>;
76			no-loopback-test = <1>;
77		};
78
79		pguclk: pguclk {
80			#clock-cells = <0>;
81			compatible = "fixed-clock";
82			clock-frequency = <25175000>;
83		};
84
85		pgu@f9000000 {
86			compatible = "snps,arcpgu";
87			reg = <0xf9000000 0x400>;
88			clocks = <&pguclk>;
89			clock-names = "pxlclk";
90		};
91
92		ps2: ps2@f9001000 {
93			compatible = "snps,arc_ps2";
94			reg = <0xf9000400 0x14>;
95			interrupts = <3 0>;
96			interrupt-parent = <&idu_intc>;
97			interrupt-names = "arc_ps2_irq";
98		};
99
100		eth0: ethernet@f0003000 {
101			compatible = "ezchip,nps-mgt-enet";
102			reg = <0xf0003000 0x44>;
103			interrupt-parent = <&idu_intc>;
104			interrupts = <1 2>;
105		};
106
107		arcpct0: pct {
108			compatible = "snps,archs-pct";
109			#interrupt-cells = <1>;
110			interrupts = <20>;
111		};
112	};
113};
114