1a12ebe16SVineet Gupta/* 2a12ebe16SVineet Gupta * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) 3a12ebe16SVineet Gupta * 4a12ebe16SVineet Gupta * This program is free software; you can redistribute it and/or modify 5a12ebe16SVineet Gupta * it under the terms of the GNU General Public License version 2 as 6a12ebe16SVineet Gupta * published by the Free Software Foundation. 7a12ebe16SVineet Gupta */ 8a12ebe16SVineet Gupta/dts-v1/; 9a12ebe16SVineet Gupta 10a12ebe16SVineet Gupta/include/ "skeleton.dtsi" 11a12ebe16SVineet Gupta 12a12ebe16SVineet Gupta/ { 13a12ebe16SVineet Gupta compatible = "snps,nsimosci_hs"; 14a12ebe16SVineet Gupta clock-frequency = <5000000>; /* 5 MHZ */ 15a12ebe16SVineet Gupta #address-cells = <1>; 16a12ebe16SVineet Gupta #size-cells = <1>; 17a12ebe16SVineet Gupta interrupt-parent = <&core_intc>; 18a12ebe16SVineet Gupta 19a12ebe16SVineet Gupta chosen { 20a12ebe16SVineet Gupta /* this is for console on serial */ 21a12ebe16SVineet Gupta bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblan=0 debug"; 22a12ebe16SVineet Gupta }; 23a12ebe16SVineet Gupta 24a12ebe16SVineet Gupta aliases { 25a12ebe16SVineet Gupta serial0 = &uart0; 26a12ebe16SVineet Gupta }; 27a12ebe16SVineet Gupta 28a12ebe16SVineet Gupta fpga { 29a12ebe16SVineet Gupta compatible = "simple-bus"; 30a12ebe16SVineet Gupta #address-cells = <1>; 31a12ebe16SVineet Gupta #size-cells = <1>; 32a12ebe16SVineet Gupta 33a12ebe16SVineet Gupta /* child and parent address space 1:1 mapped */ 34a12ebe16SVineet Gupta ranges; 35a12ebe16SVineet Gupta 36a12ebe16SVineet Gupta core_intc: core-interrupt-controller { 37a12ebe16SVineet Gupta compatible = "snps,archs-intc"; 38a12ebe16SVineet Gupta interrupt-controller; 39a12ebe16SVineet Gupta #interrupt-cells = <1>; 40a12ebe16SVineet Gupta/* interrupts = <16 17 18 19 20 21 22 23 24 25>; */ 41a12ebe16SVineet Gupta }; 42a12ebe16SVineet Gupta 43a12ebe16SVineet Gupta idu_intc: idu-interrupt-controller { 44a12ebe16SVineet Gupta compatible = "snps,archs-idu-intc"; 45a12ebe16SVineet Gupta interrupt-controller; 46a12ebe16SVineet Gupta interrupt-parent = <&core_intc>; 47a12ebe16SVineet Gupta 48a12ebe16SVineet Gupta /* 49a12ebe16SVineet Gupta * <hwirq distribution> 50a12ebe16SVineet Gupta * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 51a12ebe16SVineet Gupta */ 52a12ebe16SVineet Gupta #interrupt-cells = <2>; 53a12ebe16SVineet Gupta 54a12ebe16SVineet Gupta /* 55a12ebe16SVineet Gupta * upstream irqs to core intc - downstream these are 56a12ebe16SVineet Gupta * "COMMON" irq 0,1.. 57a12ebe16SVineet Gupta */ 58a12ebe16SVineet Gupta interrupts = <24 25 26 27 28 29 30 31>; 59a12ebe16SVineet Gupta }; 60a12ebe16SVineet Gupta 61a12ebe16SVineet Gupta uart0: serial@f0000000 { 62a12ebe16SVineet Gupta compatible = "ns8250"; 63a12ebe16SVineet Gupta reg = <0xf0000000 0x2000>; 64a12ebe16SVineet Gupta interrupt-parent = <&idu_intc>; 65a12ebe16SVineet Gupta interrupts = <0 0>; /* cmn irq 0 -> cpu irq 24 66a12ebe16SVineet Gupta RR distribute to all cpus */ 67a12ebe16SVineet Gupta clock-frequency = <3686400>; 68a12ebe16SVineet Gupta baud = <115200>; 69a12ebe16SVineet Gupta reg-shift = <2>; 70a12ebe16SVineet Gupta reg-io-width = <4>; 71a12ebe16SVineet Gupta no-loopback-test = <1>; 72a12ebe16SVineet Gupta }; 73a12ebe16SVineet Gupta 74a12ebe16SVineet Gupta pgu0: pgu@f9000000 { 75a12ebe16SVineet Gupta compatible = "snps,arcpgufb"; 76a12ebe16SVineet Gupta reg = <0xf9000000 0x400>; 77a12ebe16SVineet Gupta }; 78a12ebe16SVineet Gupta 79a12ebe16SVineet Gupta ps2: ps2@f9001000 { 80a12ebe16SVineet Gupta compatible = "snps,arc_ps2"; 81a12ebe16SVineet Gupta reg = <0xf9000400 0x14>; 82a12ebe16SVineet Gupta interrupts = <3 0>; 83a12ebe16SVineet Gupta interrupt-parent = <&idu_intc>; 84a12ebe16SVineet Gupta interrupt-names = "arc_ps2_irq"; 85a12ebe16SVineet Gupta }; 86a12ebe16SVineet Gupta 87a12ebe16SVineet Gupta eth0: ethernet@f0003000 { 88df420fd6SLada Trimasova compatible = "ezchip,nps-mgt-enet"; 89a12ebe16SVineet Gupta reg = <0xf0003000 0x44>; 90a12ebe16SVineet Gupta interrupt-parent = <&idu_intc>; 91df420fd6SLada Trimasova interrupts = <1 2>; 92a12ebe16SVineet Gupta }; 93a12ebe16SVineet Gupta 94a12ebe16SVineet Gupta arcpct0: pct { 95a12ebe16SVineet Gupta compatible = "snps,archs-pct"; 96a12ebe16SVineet Gupta #interrupt-cells = <1>; 97a12ebe16SVineet Gupta interrupts = <20>; 98a12ebe16SVineet Gupta }; 99a12ebe16SVineet Gupta }; 100a12ebe16SVineet Gupta}; 101