1a12ebe16SVineet Gupta/* 2a12ebe16SVineet Gupta * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) 3a12ebe16SVineet Gupta * 4a12ebe16SVineet Gupta * This program is free software; you can redistribute it and/or modify 5a12ebe16SVineet Gupta * it under the terms of the GNU General Public License version 2 as 6a12ebe16SVineet Gupta * published by the Free Software Foundation. 7a12ebe16SVineet Gupta */ 8a12ebe16SVineet Gupta/dts-v1/; 9a12ebe16SVineet Gupta 102e8cd938SVineet Gupta/include/ "skeleton_hs_idu.dtsi" 11a12ebe16SVineet Gupta 12a12ebe16SVineet Gupta/ { 13618a9cd0SAlexey Brodkin model = "snps,nsimosci_hs-smp"; 14a12ebe16SVineet Gupta compatible = "snps,nsimosci_hs"; 15a12ebe16SVineet Gupta #address-cells = <1>; 16a12ebe16SVineet Gupta #size-cells = <1>; 17a12ebe16SVineet Gupta interrupt-parent = <&core_intc>; 18a12ebe16SVineet Gupta 19a12ebe16SVineet Gupta chosen { 20a12ebe16SVineet Gupta /* this is for console on serial */ 218ff3afc1SAlexey Brodkin bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblan=0 debug video=640x480-24 print-fatal-signals=1"; 22a12ebe16SVineet Gupta }; 23a12ebe16SVineet Gupta 24a12ebe16SVineet Gupta aliases { 25a12ebe16SVineet Gupta serial0 = &uart0; 26a12ebe16SVineet Gupta }; 27a12ebe16SVineet Gupta 28a12ebe16SVineet Gupta fpga { 29a12ebe16SVineet Gupta compatible = "simple-bus"; 30a12ebe16SVineet Gupta #address-cells = <1>; 31a12ebe16SVineet Gupta #size-cells = <1>; 32a12ebe16SVineet Gupta 33a12ebe16SVineet Gupta /* child and parent address space 1:1 mapped */ 34a12ebe16SVineet Gupta ranges; 35a12ebe16SVineet Gupta 36b3d6aba8SVineet Gupta core_clk: core_clk { 37b3d6aba8SVineet Gupta #clock-cells = <0>; 38b3d6aba8SVineet Gupta compatible = "fixed-clock"; 39b3d6aba8SVineet Gupta clock-frequency = <5000000>; 40b3d6aba8SVineet Gupta }; 41b3d6aba8SVineet Gupta 42a12ebe16SVineet Gupta core_intc: core-interrupt-controller { 43a12ebe16SVineet Gupta compatible = "snps,archs-intc"; 44a12ebe16SVineet Gupta interrupt-controller; 45a12ebe16SVineet Gupta #interrupt-cells = <1>; 46a12ebe16SVineet Gupta }; 47a12ebe16SVineet Gupta 48a12ebe16SVineet Gupta idu_intc: idu-interrupt-controller { 49a12ebe16SVineet Gupta compatible = "snps,archs-idu-intc"; 50a12ebe16SVineet Gupta interrupt-controller; 51a12ebe16SVineet Gupta interrupt-parent = <&core_intc>; 52ec69b269SYuriy Kolerov #interrupt-cells = <1>; 53a12ebe16SVineet Gupta }; 54a12ebe16SVineet Gupta 55a12ebe16SVineet Gupta uart0: serial@f0000000 { 56a12ebe16SVineet Gupta compatible = "ns8250"; 57a12ebe16SVineet Gupta reg = <0xf0000000 0x2000>; 58a12ebe16SVineet Gupta interrupt-parent = <&idu_intc>; 59ec69b269SYuriy Kolerov interrupts = <0>; 60a12ebe16SVineet Gupta clock-frequency = <3686400>; 61a12ebe16SVineet Gupta baud = <115200>; 62a12ebe16SVineet Gupta reg-shift = <2>; 63a12ebe16SVineet Gupta reg-io-width = <4>; 64a12ebe16SVineet Gupta no-loopback-test = <1>; 65a12ebe16SVineet Gupta }; 66a12ebe16SVineet Gupta 67830c6578SAlexey Brodkin pguclk: pguclk { 68830c6578SAlexey Brodkin #clock-cells = <0>; 69830c6578SAlexey Brodkin compatible = "fixed-clock"; 70830c6578SAlexey Brodkin clock-frequency = <25175000>; 71830c6578SAlexey Brodkin }; 72830c6578SAlexey Brodkin 73830c6578SAlexey Brodkin pgu@f9000000 { 74830c6578SAlexey Brodkin compatible = "snps,arcpgu"; 75a12ebe16SVineet Gupta reg = <0xf9000000 0x400>; 76830c6578SAlexey Brodkin clocks = <&pguclk>; 77830c6578SAlexey Brodkin clock-names = "pxlclk"; 78a12ebe16SVineet Gupta }; 79a12ebe16SVineet Gupta 80a12ebe16SVineet Gupta ps2: ps2@f9001000 { 81a12ebe16SVineet Gupta compatible = "snps,arc_ps2"; 82a12ebe16SVineet Gupta reg = <0xf9000400 0x14>; 83ec69b269SYuriy Kolerov interrupts = <3>; 84a12ebe16SVineet Gupta interrupt-parent = <&idu_intc>; 85a12ebe16SVineet Gupta interrupt-names = "arc_ps2_irq"; 86a12ebe16SVineet Gupta }; 87a12ebe16SVineet Gupta 88a12ebe16SVineet Gupta eth0: ethernet@f0003000 { 89df420fd6SLada Trimasova compatible = "ezchip,nps-mgt-enet"; 90a12ebe16SVineet Gupta reg = <0xf0003000 0x44>; 91a12ebe16SVineet Gupta interrupt-parent = <&idu_intc>; 92ec69b269SYuriy Kolerov interrupts = <1>; 93a12ebe16SVineet Gupta }; 94a12ebe16SVineet Gupta 95a12ebe16SVineet Gupta arcpct0: pct { 96a12ebe16SVineet Gupta compatible = "snps,archs-pct"; 97a12ebe16SVineet Gupta #interrupt-cells = <1>; 98a12ebe16SVineet Gupta interrupts = <20>; 99a12ebe16SVineet Gupta }; 100a12ebe16SVineet Gupta }; 101a12ebe16SVineet Gupta}; 102