1/* 2 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8/dts-v1/; 9 10/include/ "skeleton.dtsi" 11 12/ { 13 model = "snps,nsimosci"; 14 compatible = "snps,nsimosci"; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 interrupt-parent = <&core_intc>; 18 19 chosen { 20 /* this is for console on PGU */ 21 /* bootargs = "console=tty0 consoleblank=0"; */ 22 /* this is for console on serial */ 23 bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug video=640x480-24"; 24 }; 25 26 aliases { 27 serial0 = &uart0; 28 }; 29 30 fpga { 31 compatible = "simple-bus"; 32 #address-cells = <1>; 33 #size-cells = <1>; 34 35 /* child and parent address space 1:1 mapped */ 36 ranges; 37 38 core_clk: core_clk { 39 #clock-cells = <0>; 40 compatible = "fixed-clock"; 41 clock-frequency = <20000000>; 42 }; 43 44 core_intc: interrupt-controller { 45 compatible = "snps,arc700-intc"; 46 interrupt-controller; 47 #interrupt-cells = <1>; 48 }; 49 50 uart0: serial@f0000000 { 51 compatible = "ns8250"; 52 reg = <0xf0000000 0x2000>; 53 interrupts = <11>; 54 clock-frequency = <3686400>; 55 baud = <115200>; 56 reg-shift = <2>; 57 reg-io-width = <4>; 58 no-loopback-test = <1>; 59 }; 60 61 pguclk: pguclk { 62 #clock-cells = <0>; 63 compatible = "fixed-clock"; 64 clock-frequency = <25175000>; 65 }; 66 67 pgu@f9000000 { 68 compatible = "snps,arcpgu"; 69 reg = <0xf9000000 0x400>; 70 clocks = <&pguclk>; 71 clock-names = "pxlclk"; 72 }; 73 74 ps2: ps2@f9001000 { 75 compatible = "snps,arc_ps2"; 76 reg = <0xf9000400 0x14>; 77 interrupts = <13>; 78 interrupt-names = "arc_ps2_irq"; 79 }; 80 81 eth0: ethernet@f0003000 { 82 compatible = "ezchip,nps-mgt-enet"; 83 reg = <0xf0003000 0x44>; 84 interrupts = <7>; 85 }; 86 87 arcpct0: pct { 88 compatible = "snps,arc700-pct"; 89 }; 90 }; 91}; 92