1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com) 4 */ 5 6/* 7 * Device Tree for ARC HS Development Kit 8 */ 9/dts-v1/; 10 11#include <dt-bindings/reset/snps,hsdk-reset.h> 12 13/ { 14 model = "snps,hsdk"; 15 compatible = "snps,hsdk"; 16 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 chosen { 21 bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; 22 }; 23 24 aliases { 25 ethernet = &gmac; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 cpu@0 { 33 device_type = "cpu"; 34 compatible = "snps,archs38"; 35 reg = <0>; 36 clocks = <&core_clk>; 37 }; 38 39 cpu@1 { 40 device_type = "cpu"; 41 compatible = "snps,archs38"; 42 reg = <1>; 43 clocks = <&core_clk>; 44 }; 45 46 cpu@2 { 47 device_type = "cpu"; 48 compatible = "snps,archs38"; 49 reg = <2>; 50 clocks = <&core_clk>; 51 }; 52 53 cpu@3 { 54 device_type = "cpu"; 55 compatible = "snps,archs38"; 56 reg = <3>; 57 clocks = <&core_clk>; 58 }; 59 }; 60 61 input_clk: input-clk { 62 #clock-cells = <0>; 63 compatible = "fixed-clock"; 64 clock-frequency = <33333333>; 65 }; 66 67 cpu_intc: cpu-interrupt-controller { 68 compatible = "snps,archs-intc"; 69 interrupt-controller; 70 #interrupt-cells = <1>; 71 }; 72 73 idu_intc: idu-interrupt-controller { 74 compatible = "snps,archs-idu-intc"; 75 interrupt-controller; 76 #interrupt-cells = <1>; 77 interrupt-parent = <&cpu_intc>; 78 }; 79 80 arcpct: pct { 81 compatible = "snps,archs-pct"; 82 }; 83 84 /* TIMER0 with interrupt for clockevent */ 85 timer { 86 compatible = "snps,arc-timer"; 87 interrupts = <16>; 88 interrupt-parent = <&cpu_intc>; 89 clocks = <&core_clk>; 90 }; 91 92 /* 64-bit Global Free Running Counter */ 93 gfrc { 94 compatible = "snps,archs-timer-gfrc"; 95 clocks = <&core_clk>; 96 }; 97 98 soc { 99 compatible = "simple-bus"; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 interrupt-parent = <&idu_intc>; 103 104 ranges = <0x00000000 0x0 0xf0000000 0x10000000>; 105 106 cgu_rst: reset-controller@8a0 { 107 compatible = "snps,hsdk-reset"; 108 #reset-cells = <1>; 109 reg = <0x8a0 0x4>, <0xff0 0x4>; 110 }; 111 112 core_clk: core-clk@0 { 113 compatible = "snps,hsdk-core-pll-clock"; 114 reg = <0x00 0x10>, <0x14b8 0x4>; 115 #clock-cells = <0>; 116 clocks = <&input_clk>; 117 118 /* 119 * Set initial core pll output frequency to 1GHz. 120 * It will be applied at the core pll driver probing 121 * on early boot. 122 */ 123 assigned-clocks = <&core_clk>; 124 assigned-clock-rates = <1000000000>; 125 }; 126 127 serial: serial@5000 { 128 compatible = "snps,dw-apb-uart"; 129 reg = <0x5000 0x100>; 130 clock-frequency = <33330000>; 131 interrupts = <6>; 132 baud = <115200>; 133 reg-shift = <2>; 134 reg-io-width = <4>; 135 }; 136 137 gmacclk: gmacclk { 138 compatible = "fixed-clock"; 139 clock-frequency = <400000000>; 140 #clock-cells = <0>; 141 }; 142 143 mmcclk_ciu: mmcclk-ciu { 144 compatible = "fixed-clock"; 145 /* 146 * DW sdio controller has external ciu clock divider 147 * controlled via register in SDIO IP. Due to its 148 * unexpected default value (it should divide by 1 149 * but it divides by 8) SDIO IP uses wrong clock and 150 * works unstable (see STAR 9001204800) 151 * We switched to the minimum possible value of the 152 * divisor (div-by-2) in HSDK platform code. 153 * So add temporary fix and change clock frequency 154 * to 50000000 Hz until we fix dw sdio driver itself. 155 */ 156 clock-frequency = <50000000>; 157 #clock-cells = <0>; 158 }; 159 160 mmcclk_biu: mmcclk-biu { 161 compatible = "fixed-clock"; 162 clock-frequency = <400000000>; 163 #clock-cells = <0>; 164 }; 165 166 gpu_core_clk: gpu-core-clk { 167 compatible = "fixed-clock"; 168 clock-frequency = <400000000>; 169 #clock-cells = <0>; 170 }; 171 172 gpu_dma_clk: gpu-dma-clk { 173 compatible = "fixed-clock"; 174 clock-frequency = <400000000>; 175 #clock-cells = <0>; 176 }; 177 178 gpu_cfg_clk: gpu-cfg-clk { 179 compatible = "fixed-clock"; 180 clock-frequency = <200000000>; 181 #clock-cells = <0>; 182 }; 183 184 dmac_core_clk: dmac-core-clk { 185 compatible = "fixed-clock"; 186 clock-frequency = <400000000>; 187 #clock-cells = <0>; 188 }; 189 190 dmac_cfg_clk: dmac-gpu-cfg-clk { 191 compatible = "fixed-clock"; 192 clock-frequency = <200000000>; 193 #clock-cells = <0>; 194 }; 195 196 gmac: ethernet@8000 { 197 #interrupt-cells = <1>; 198 compatible = "snps,dwmac"; 199 reg = <0x8000 0x2000>; 200 interrupts = <10>; 201 interrupt-names = "macirq"; 202 phy-mode = "rgmii"; 203 snps,pbl = <32>; 204 snps,multicast-filter-bins = <256>; 205 clocks = <&gmacclk>; 206 clock-names = "stmmaceth"; 207 phy-handle = <&phy0>; 208 resets = <&cgu_rst HSDK_ETH_RESET>; 209 reset-names = "stmmaceth"; 210 mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */ 211 dma-coherent; 212 213 tx-fifo-depth = <4096>; 214 rx-fifo-depth = <4096>; 215 216 mdio { 217 #address-cells = <1>; 218 #size-cells = <0>; 219 compatible = "snps,dwmac-mdio"; 220 phy0: ethernet-phy@0 { 221 reg = <0>; 222 }; 223 }; 224 }; 225 226 ohci@60000 { 227 compatible = "snps,hsdk-v1.0-ohci", "generic-ohci"; 228 reg = <0x60000 0x100>; 229 interrupts = <15>; 230 resets = <&cgu_rst HSDK_USB_RESET>; 231 dma-coherent; 232 }; 233 234 ehci@40000 { 235 compatible = "snps,hsdk-v1.0-ehci", "generic-ehci"; 236 reg = <0x40000 0x100>; 237 interrupts = <15>; 238 resets = <&cgu_rst HSDK_USB_RESET>; 239 dma-coherent; 240 }; 241 242 mmc@a000 { 243 compatible = "altr,socfpga-dw-mshc"; 244 reg = <0xa000 0x400>; 245 num-slots = <1>; 246 fifo-depth = <16>; 247 card-detect-delay = <200>; 248 clocks = <&mmcclk_biu>, <&mmcclk_ciu>; 249 clock-names = "biu", "ciu"; 250 interrupts = <12>; 251 bus-width = <4>; 252 dma-coherent; 253 }; 254 255 creg_gpio: gpio@14b0 { 256 compatible = "snps,creg-gpio-hsdk"; 257 reg = <0x14b0 0x4>; 258 gpio-controller; 259 #gpio-cells = <2>; 260 ngpios = <2>; 261 }; 262 263 gpio: gpio@3000 { 264 compatible = "snps,dw-apb-gpio"; 265 reg = <0x3000 0x20>; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 269 gpio_port_a: gpio-controller@0 { 270 compatible = "snps,dw-apb-gpio-port"; 271 gpio-controller; 272 #gpio-cells = <2>; 273 snps,nr-gpios = <24>; 274 reg = <0>; 275 }; 276 }; 277 278 gpu_3d: gpu@90000 { 279 compatible = "vivante,gc"; 280 reg = <0x90000 0x4000>; 281 clocks = <&gpu_dma_clk>, 282 <&gpu_cfg_clk>, 283 <&gpu_core_clk>, 284 <&gpu_core_clk>; 285 clock-names = "bus", "reg", "core", "shader"; 286 interrupts = <28>; 287 }; 288 289 dmac: dmac@80000 { 290 compatible = "snps,axi-dma-1.01a"; 291 reg = <0x80000 0x400>; 292 interrupts = <27>; 293 clocks = <&dmac_core_clk>, <&dmac_cfg_clk>; 294 clock-names = "core-clk", "cfgr-clk"; 295 296 dma-channels = <4>; 297 snps,dma-masters = <2>; 298 snps,data-width = <3>; 299 snps,block-size = <4096 4096 4096 4096>; 300 snps,priority = <0 1 2 3>; 301 snps,axi-max-burst-len = <16>; 302 }; 303 }; 304 305 memory@80000000 { 306 #address-cells = <2>; 307 #size-cells = <2>; 308 device_type = "memory"; 309 reg = <0x0 0x80000000 0x0 0x40000000>; /* 1 GB lowmem */ 310 /* 0x1 0x00000000 0x0 0x40000000>; 1 GB highmem */ 311 }; 312}; 313