1/* 2 * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9/* 10 * Device Tree for ARC HS Development Kit 11 */ 12/dts-v1/; 13 14#include <dt-bindings/net/ti-dp83867.h> 15#include <dt-bindings/reset/snps,hsdk-reset.h> 16 17/ { 18 model = "snps,hsdk"; 19 compatible = "snps,hsdk"; 20 21 #address-cells = <1>; 22 #size-cells = <1>; 23 24 chosen { 25 bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; 26 }; 27 28 aliases { 29 ethernet = &gmac; 30 }; 31 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 cpu@0 { 37 device_type = "cpu"; 38 compatible = "snps,archs38"; 39 reg = <0>; 40 clocks = <&core_clk>; 41 }; 42 43 cpu@1 { 44 device_type = "cpu"; 45 compatible = "snps,archs38"; 46 reg = <1>; 47 clocks = <&core_clk>; 48 }; 49 50 cpu@2 { 51 device_type = "cpu"; 52 compatible = "snps,archs38"; 53 reg = <2>; 54 clocks = <&core_clk>; 55 }; 56 57 cpu@3 { 58 device_type = "cpu"; 59 compatible = "snps,archs38"; 60 reg = <3>; 61 clocks = <&core_clk>; 62 }; 63 }; 64 65 input_clk: input-clk { 66 #clock-cells = <0>; 67 compatible = "fixed-clock"; 68 clock-frequency = <33333333>; 69 }; 70 71 cpu_intc: cpu-interrupt-controller { 72 compatible = "snps,archs-intc"; 73 interrupt-controller; 74 #interrupt-cells = <1>; 75 }; 76 77 idu_intc: idu-interrupt-controller { 78 compatible = "snps,archs-idu-intc"; 79 interrupt-controller; 80 #interrupt-cells = <1>; 81 interrupt-parent = <&cpu_intc>; 82 }; 83 84 arcpct: pct { 85 compatible = "snps,archs-pct"; 86 }; 87 88 /* TIMER0 with interrupt for clockevent */ 89 timer { 90 compatible = "snps,arc-timer"; 91 interrupts = <16>; 92 interrupt-parent = <&cpu_intc>; 93 clocks = <&core_clk>; 94 }; 95 96 /* 64-bit Global Free Running Counter */ 97 gfrc { 98 compatible = "snps,archs-timer-gfrc"; 99 clocks = <&core_clk>; 100 }; 101 102 soc { 103 compatible = "simple-bus"; 104 #address-cells = <1>; 105 #size-cells = <1>; 106 interrupt-parent = <&idu_intc>; 107 108 ranges = <0x00000000 0xf0000000 0x10000000>; 109 110 cgu_rst: reset-controller@8a0 { 111 compatible = "snps,hsdk-reset"; 112 #reset-cells = <1>; 113 reg = <0x8A0 0x4>, <0xFF0 0x4>; 114 }; 115 116 core_clk: core-clk@0 { 117 compatible = "snps,hsdk-core-pll-clock"; 118 reg = <0x00 0x10>, <0x14B8 0x4>; 119 #clock-cells = <0>; 120 clocks = <&input_clk>; 121 122 /* 123 * Set initial core pll output frequency to 1GHz. 124 * It will be applied at the core pll driver probing 125 * on early boot. 126 */ 127 assigned-clocks = <&core_clk>; 128 assigned-clock-rates = <1000000000>; 129 }; 130 131 serial: serial@5000 { 132 compatible = "snps,dw-apb-uart"; 133 reg = <0x5000 0x100>; 134 clock-frequency = <33330000>; 135 interrupts = <6>; 136 baud = <115200>; 137 reg-shift = <2>; 138 reg-io-width = <4>; 139 }; 140 141 gmacclk: gmacclk { 142 compatible = "fixed-clock"; 143 clock-frequency = <400000000>; 144 #clock-cells = <0>; 145 }; 146 147 mmcclk_ciu: mmcclk-ciu { 148 compatible = "fixed-clock"; 149 /* 150 * DW sdio controller has external ciu clock divider 151 * controlled via register in SDIO IP. Due to its 152 * unexpected default value (it should divide by 1 153 * but it divides by 8) SDIO IP uses wrong clock and 154 * works unstable (see STAR 9001204800) 155 * We switched to the minimum possible value of the 156 * divisor (div-by-2) in HSDK platform code. 157 * So add temporary fix and change clock frequency 158 * to 50000000 Hz until we fix dw sdio driver itself. 159 */ 160 clock-frequency = <50000000>; 161 #clock-cells = <0>; 162 }; 163 164 mmcclk_biu: mmcclk-biu { 165 compatible = "fixed-clock"; 166 clock-frequency = <400000000>; 167 #clock-cells = <0>; 168 }; 169 170 gmac: ethernet@8000 { 171 #interrupt-cells = <1>; 172 compatible = "snps,dwmac"; 173 reg = <0x8000 0x2000>; 174 interrupts = <10>; 175 interrupt-names = "macirq"; 176 phy-mode = "rgmii"; 177 snps,pbl = <32>; 178 clocks = <&gmacclk>; 179 clock-names = "stmmaceth"; 180 phy-handle = <&phy0>; 181 resets = <&cgu_rst HSDK_ETH_RESET>; 182 reset-names = "stmmaceth"; 183 mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */ 184 dma-coherent; 185 186 mdio { 187 #address-cells = <1>; 188 #size-cells = <0>; 189 compatible = "snps,dwmac-mdio"; 190 phy0: ethernet-phy@0 { 191 reg = <0>; 192 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 193 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 194 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 195 }; 196 }; 197 }; 198 199 ohci@60000 { 200 compatible = "snps,hsdk-v1.0-ohci", "generic-ohci"; 201 reg = <0x60000 0x100>; 202 interrupts = <15>; 203 dma-coherent; 204 }; 205 206 ehci@40000 { 207 compatible = "snps,hsdk-v1.0-ehci", "generic-ehci"; 208 reg = <0x40000 0x100>; 209 interrupts = <15>; 210 dma-coherent; 211 }; 212 213 mmc@a000 { 214 compatible = "altr,socfpga-dw-mshc"; 215 reg = <0xa000 0x400>; 216 num-slots = <1>; 217 fifo-depth = <16>; 218 card-detect-delay = <200>; 219 clocks = <&mmcclk_biu>, <&mmcclk_ciu>; 220 clock-names = "biu", "ciu"; 221 interrupts = <12>; 222 bus-width = <4>; 223 dma-coherent; 224 }; 225 226 gpio: gpio@3000 { 227 compatible = "snps,dw-apb-gpio"; 228 reg = <0x3000 0x20>; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 232 gpio_port_a: gpio-controller@0 { 233 compatible = "snps,dw-apb-gpio-port"; 234 gpio-controller; 235 #gpio-cells = <2>; 236 snps,nr-gpios = <24>; 237 reg = <0>; 238 }; 239 }; 240 }; 241 242 memory@80000000 { 243 #address-cells = <1>; 244 #size-cells = <1>; 245 device_type = "memory"; 246 reg = <0x80000000 0x40000000>; /* 1 GiB */ 247 }; 248}; 249