1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com) 4 */ 5 6/* 7 * Device Tree for ARC HS Development Kit 8 */ 9/dts-v1/; 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/reset/snps,hsdk-reset.h> 13 14/ { 15 model = "snps,hsdk"; 16 compatible = "snps,hsdk"; 17 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 chosen { 22 bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; 23 }; 24 25 aliases { 26 ethernet = &gmac; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu@0 { 34 device_type = "cpu"; 35 compatible = "snps,archs38"; 36 reg = <0>; 37 clocks = <&core_clk>; 38 }; 39 40 cpu@1 { 41 device_type = "cpu"; 42 compatible = "snps,archs38"; 43 reg = <1>; 44 clocks = <&core_clk>; 45 }; 46 47 cpu@2 { 48 device_type = "cpu"; 49 compatible = "snps,archs38"; 50 reg = <2>; 51 clocks = <&core_clk>; 52 }; 53 54 cpu@3 { 55 device_type = "cpu"; 56 compatible = "snps,archs38"; 57 reg = <3>; 58 clocks = <&core_clk>; 59 }; 60 }; 61 62 input_clk: input-clk { 63 #clock-cells = <0>; 64 compatible = "fixed-clock"; 65 clock-frequency = <33333333>; 66 }; 67 68 cpu_intc: cpu-interrupt-controller { 69 compatible = "snps,archs-intc"; 70 interrupt-controller; 71 #interrupt-cells = <1>; 72 }; 73 74 idu_intc: idu-interrupt-controller { 75 compatible = "snps,archs-idu-intc"; 76 interrupt-controller; 77 #interrupt-cells = <1>; 78 interrupt-parent = <&cpu_intc>; 79 }; 80 81 arcpct: pct { 82 compatible = "snps,archs-pct"; 83 }; 84 85 /* TIMER0 with interrupt for clockevent */ 86 timer { 87 compatible = "snps,arc-timer"; 88 interrupts = <16>; 89 interrupt-parent = <&cpu_intc>; 90 clocks = <&core_clk>; 91 }; 92 93 /* 64-bit Global Free Running Counter */ 94 gfrc { 95 compatible = "snps,archs-timer-gfrc"; 96 clocks = <&core_clk>; 97 }; 98 99 soc { 100 compatible = "simple-bus"; 101 #address-cells = <1>; 102 #size-cells = <1>; 103 interrupt-parent = <&idu_intc>; 104 105 ranges = <0x00000000 0x0 0xf0000000 0x10000000>; 106 107 cgu_rst: reset-controller@8a0 { 108 compatible = "snps,hsdk-reset"; 109 #reset-cells = <1>; 110 reg = <0x8a0 0x4>, <0xff0 0x4>; 111 }; 112 113 core_clk: core-clk@0 { 114 compatible = "snps,hsdk-core-pll-clock"; 115 reg = <0x00 0x10>, <0x14b8 0x4>; 116 #clock-cells = <0>; 117 clocks = <&input_clk>; 118 119 /* 120 * Set initial core pll output frequency to 1GHz. 121 * It will be applied at the core pll driver probing 122 * on early boot. 123 */ 124 assigned-clocks = <&core_clk>; 125 assigned-clock-rates = <1000000000>; 126 }; 127 128 serial: serial@5000 { 129 compatible = "snps,dw-apb-uart"; 130 reg = <0x5000 0x100>; 131 clock-frequency = <33330000>; 132 interrupts = <6>; 133 baud = <115200>; 134 reg-shift = <2>; 135 reg-io-width = <4>; 136 }; 137 138 gmacclk: gmacclk { 139 compatible = "fixed-clock"; 140 clock-frequency = <400000000>; 141 #clock-cells = <0>; 142 }; 143 144 mmcclk_ciu: mmcclk-ciu { 145 compatible = "fixed-clock"; 146 /* 147 * DW sdio controller has external ciu clock divider 148 * controlled via register in SDIO IP. Due to its 149 * unexpected default value (it should divide by 1 150 * but it divides by 8) SDIO IP uses wrong clock and 151 * works unstable (see STAR 9001204800) 152 * We switched to the minimum possible value of the 153 * divisor (div-by-2) in HSDK platform code. 154 * So add temporary fix and change clock frequency 155 * to 50000000 Hz until we fix dw sdio driver itself. 156 */ 157 clock-frequency = <50000000>; 158 #clock-cells = <0>; 159 }; 160 161 mmcclk_biu: mmcclk-biu { 162 compatible = "fixed-clock"; 163 clock-frequency = <400000000>; 164 #clock-cells = <0>; 165 }; 166 167 gpu_core_clk: gpu-core-clk { 168 compatible = "fixed-clock"; 169 clock-frequency = <400000000>; 170 #clock-cells = <0>; 171 }; 172 173 gpu_dma_clk: gpu-dma-clk { 174 compatible = "fixed-clock"; 175 clock-frequency = <400000000>; 176 #clock-cells = <0>; 177 }; 178 179 gpu_cfg_clk: gpu-cfg-clk { 180 compatible = "fixed-clock"; 181 clock-frequency = <200000000>; 182 #clock-cells = <0>; 183 }; 184 185 dmac_core_clk: dmac-core-clk { 186 compatible = "fixed-clock"; 187 clock-frequency = <400000000>; 188 #clock-cells = <0>; 189 }; 190 191 dmac_cfg_clk: dmac-gpu-cfg-clk { 192 compatible = "fixed-clock"; 193 clock-frequency = <200000000>; 194 #clock-cells = <0>; 195 }; 196 197 gmac: ethernet@8000 { 198 #interrupt-cells = <1>; 199 compatible = "snps,dwmac"; 200 reg = <0x8000 0x2000>; 201 interrupts = <10>; 202 interrupt-names = "macirq"; 203 phy-mode = "rgmii"; 204 snps,pbl = <32>; 205 snps,multicast-filter-bins = <256>; 206 clocks = <&gmacclk>; 207 clock-names = "stmmaceth"; 208 phy-handle = <&phy0>; 209 resets = <&cgu_rst HSDK_ETH_RESET>; 210 reset-names = "stmmaceth"; 211 mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */ 212 dma-coherent; 213 214 tx-fifo-depth = <4096>; 215 rx-fifo-depth = <4096>; 216 217 mdio { 218 #address-cells = <1>; 219 #size-cells = <0>; 220 compatible = "snps,dwmac-mdio"; 221 phy0: ethernet-phy@0 { 222 reg = <0>; 223 }; 224 }; 225 }; 226 227 ohci@60000 { 228 compatible = "snps,hsdk-v1.0-ohci", "generic-ohci"; 229 reg = <0x60000 0x100>; 230 interrupts = <15>; 231 resets = <&cgu_rst HSDK_USB_RESET>; 232 dma-coherent; 233 }; 234 235 ehci@40000 { 236 compatible = "snps,hsdk-v1.0-ehci", "generic-ehci"; 237 reg = <0x40000 0x100>; 238 interrupts = <15>; 239 resets = <&cgu_rst HSDK_USB_RESET>; 240 dma-coherent; 241 }; 242 243 mmc@a000 { 244 compatible = "altr,socfpga-dw-mshc"; 245 reg = <0xa000 0x400>; 246 num-slots = <1>; 247 fifo-depth = <16>; 248 card-detect-delay = <200>; 249 clocks = <&mmcclk_biu>, <&mmcclk_ciu>; 250 clock-names = "biu", "ciu"; 251 interrupts = <12>; 252 bus-width = <4>; 253 dma-coherent; 254 }; 255 256 spi0: spi@20000 { 257 compatible = "snps,dw-apb-ssi"; 258 reg = <0x20000 0x100>; 259 #address-cells = <1>; 260 #size-cells = <0>; 261 interrupts = <16>; 262 num-cs = <2>; 263 reg-io-width = <4>; 264 clocks = <&input_clk>; 265 cs-gpios = <&creg_gpio 0 GPIO_ACTIVE_LOW>, 266 <&creg_gpio 1 GPIO_ACTIVE_LOW>; 267 }; 268 269 creg_gpio: gpio@14b0 { 270 compatible = "snps,creg-gpio-hsdk"; 271 reg = <0x14b0 0x4>; 272 gpio-controller; 273 #gpio-cells = <2>; 274 ngpios = <2>; 275 }; 276 277 gpio: gpio@3000 { 278 compatible = "snps,dw-apb-gpio"; 279 reg = <0x3000 0x20>; 280 #address-cells = <1>; 281 #size-cells = <0>; 282 283 gpio_port_a: gpio-controller@0 { 284 compatible = "snps,dw-apb-gpio-port"; 285 gpio-controller; 286 #gpio-cells = <2>; 287 snps,nr-gpios = <24>; 288 reg = <0>; 289 }; 290 }; 291 292 gpu_3d: gpu@90000 { 293 compatible = "vivante,gc"; 294 reg = <0x90000 0x4000>; 295 clocks = <&gpu_dma_clk>, 296 <&gpu_cfg_clk>, 297 <&gpu_core_clk>, 298 <&gpu_core_clk>; 299 clock-names = "bus", "reg", "core", "shader"; 300 interrupts = <28>; 301 }; 302 303 dmac: dmac@80000 { 304 compatible = "snps,axi-dma-1.01a"; 305 reg = <0x80000 0x400>; 306 interrupts = <27>; 307 clocks = <&dmac_core_clk>, <&dmac_cfg_clk>; 308 clock-names = "core-clk", "cfgr-clk"; 309 310 dma-channels = <4>; 311 snps,dma-masters = <2>; 312 snps,data-width = <3>; 313 snps,block-size = <4096 4096 4096 4096>; 314 snps,priority = <0 1 2 3>; 315 snps,axi-max-burst-len = <16>; 316 }; 317 }; 318 319 memory@80000000 { 320 #address-cells = <2>; 321 #size-cells = <2>; 322 device_type = "memory"; 323 reg = <0x0 0x80000000 0x0 0x40000000>; /* 1 GB lowmem */ 324 /* 0x1 0x00000000 0x0 0x40000000>; 1 GB highmem */ 325 }; 326}; 327