1/* 2 * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9/* 10 * Device Tree for ARC HS Development Kit 11 */ 12/dts-v1/; 13 14#include <dt-bindings/net/ti-dp83867.h> 15 16/ { 17 model = "snps,hsdk"; 18 compatible = "snps,hsdk"; 19 20 #address-cells = <1>; 21 #size-cells = <1>; 22 23 chosen { 24 bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu@0 { 32 device_type = "cpu"; 33 compatible = "snps,archs38"; 34 reg = <0>; 35 clocks = <&core_clk>; 36 }; 37 38 cpu@1 { 39 device_type = "cpu"; 40 compatible = "snps,archs38"; 41 reg = <1>; 42 clocks = <&core_clk>; 43 }; 44 45 cpu@2 { 46 device_type = "cpu"; 47 compatible = "snps,archs38"; 48 reg = <2>; 49 clocks = <&core_clk>; 50 }; 51 52 cpu@3 { 53 device_type = "cpu"; 54 compatible = "snps,archs38"; 55 reg = <3>; 56 clocks = <&core_clk>; 57 }; 58 }; 59 60 core_clk: core-clk { 61 #clock-cells = <0>; 62 compatible = "fixed-clock"; 63 clock-frequency = <500000000>; 64 }; 65 66 cpu_intc: cpu-interrupt-controller { 67 compatible = "snps,archs-intc"; 68 interrupt-controller; 69 #interrupt-cells = <1>; 70 }; 71 72 idu_intc: idu-interrupt-controller { 73 compatible = "snps,archs-idu-intc"; 74 interrupt-controller; 75 #interrupt-cells = <1>; 76 interrupt-parent = <&cpu_intc>; 77 }; 78 79 arcpct: pct { 80 compatible = "snps,archs-pct"; 81 }; 82 83 /* TIMER0 with interrupt for clockevent */ 84 timer { 85 compatible = "snps,arc-timer"; 86 interrupts = <16>; 87 interrupt-parent = <&cpu_intc>; 88 clocks = <&core_clk>; 89 }; 90 91 /* 64-bit Global Free Running Counter */ 92 gfrc { 93 compatible = "snps,archs-timer-gfrc"; 94 clocks = <&core_clk>; 95 }; 96 97 soc { 98 compatible = "simple-bus"; 99 #address-cells = <1>; 100 #size-cells = <1>; 101 interrupt-parent = <&idu_intc>; 102 103 ranges = <0x00000000 0xf0000000 0x10000000>; 104 105 serial: serial@5000 { 106 compatible = "snps,dw-apb-uart"; 107 reg = <0x5000 0x100>; 108 clock-frequency = <33330000>; 109 interrupts = <6>; 110 baud = <115200>; 111 reg-shift = <2>; 112 reg-io-width = <4>; 113 }; 114 115 gmacclk: gmacclk { 116 compatible = "fixed-clock"; 117 clock-frequency = <400000000>; 118 #clock-cells = <0>; 119 }; 120 121 mmcclk_ciu: mmcclk-ciu { 122 compatible = "fixed-clock"; 123 clock-frequency = <100000000>; 124 #clock-cells = <0>; 125 }; 126 127 mmcclk_biu: mmcclk-biu { 128 compatible = "fixed-clock"; 129 clock-frequency = <400000000>; 130 #clock-cells = <0>; 131 }; 132 133 ethernet@8000 { 134 #interrupt-cells = <1>; 135 compatible = "snps,dwmac"; 136 reg = <0x8000 0x2000>; 137 interrupts = <10>; 138 interrupt-names = "macirq"; 139 phy-mode = "rgmii"; 140 snps,pbl = <32>; 141 clocks = <&gmacclk>; 142 clock-names = "stmmaceth"; 143 phy-handle = <&phy0>; 144 145 mdio { 146 #address-cells = <1>; 147 #size-cells = <0>; 148 compatible = "snps,dwmac-mdio"; 149 phy0: ethernet-phy@0 { 150 reg = <0>; 151 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 152 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 153 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 154 }; 155 }; 156 }; 157 158 ohci@60000 { 159 compatible = "snps,hsdk-v1.0-ohci", "generic-ohci"; 160 reg = <0x60000 0x100>; 161 interrupts = <15>; 162 }; 163 164 ehci@40000 { 165 compatible = "snps,hsdk-v1.0-ehci", "generic-ehci"; 166 reg = <0x40000 0x100>; 167 interrupts = <15>; 168 }; 169 170 mmc@a000 { 171 compatible = "altr,socfpga-dw-mshc"; 172 reg = <0xa000 0x400>; 173 num-slots = <1>; 174 fifo-depth = <16>; 175 card-detect-delay = <200>; 176 clocks = <&mmcclk_biu>, <&mmcclk_ciu>; 177 clock-names = "biu", "ciu"; 178 interrupts = <12>; 179 bus-width = <4>; 180 }; 181 }; 182 183 memory@80000000 { 184 #address-cells = <1>; 185 #size-cells = <1>; 186 device_type = "memory"; 187 reg = <0x80000000 0x40000000>; /* 1 GiB */ 188 }; 189}; 190