1/* 2 * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8/dts-v1/; 9 10/include/ "skeleton_hs.dtsi" 11 12/ { 13 model = "snps,zebu_hs"; 14 compatible = "snps,zebu_hs"; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 interrupt-parent = <&core_intc>; 18 19 memory { 20 device_type = "memory"; 21 reg = <0x80000000 0x20000000>; /* 512 */ 22 }; 23 24 chosen { 25 bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; 26 }; 27 28 aliases { 29 serial0 = &uart0; 30 }; 31 32 fpga { 33 compatible = "simple-bus"; 34 #address-cells = <1>; 35 #size-cells = <1>; 36 37 /* child and parent address space 1:1 mapped */ 38 ranges; 39 40 core_clk: core_clk { 41 #clock-cells = <0>; 42 compatible = "fixed-clock"; 43 clock-frequency = <50000000>; 44 }; 45 46 core_intc: interrupt-controller { 47 compatible = "snps,archs-intc"; 48 interrupt-controller; 49 #interrupt-cells = <1>; 50 }; 51 52 uart0: serial@f0000000 { 53 compatible = "ns8250"; 54 reg = <0xf0000000 0x2000>; 55 interrupts = <24>; 56 clock-frequency = <50000000>; 57 baud = <115200>; 58 reg-shift = <2>; 59 reg-io-width = <4>; 60 no-loopback-test = <1>; 61 }; 62 63 arcpct0: pct { 64 compatible = "snps,archs-pct"; 65 #interrupt-cells = <1>; 66 interrupts = <20>; 67 }; 68 }; 69}; 70