1/* 2 * Support for peripherals on the AXS10x mainboard 3 * 4 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11/ { 12 aliases { 13 ethernet = &gmac; 14 }; 15 16 axs10x_mb { 17 compatible = "simple-bus"; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 ranges = <0x00000000 0x0 0xe0000000 0x10000000>; 21 interrupt-parent = <&mb_intc>; 22 23 creg_rst: reset-controller@11220 { 24 compatible = "snps,axs10x-reset"; 25 #reset-cells = <1>; 26 reg = <0x11220 0x4>; 27 }; 28 29 i2sclk: i2sclk@100a0 { 30 compatible = "snps,axs10x-i2s-pll-clock"; 31 reg = <0x100a0 0x10>; 32 clocks = <&i2spll_clk>; 33 #clock-cells = <0>; 34 }; 35 36 clocks { 37 i2spll_clk: i2spll_clk { 38 compatible = "fixed-clock"; 39 clock-frequency = <27000000>; 40 #clock-cells = <0>; 41 }; 42 43 i2cclk: i2cclk { 44 compatible = "fixed-clock"; 45 clock-frequency = <50000000>; 46 #clock-cells = <0>; 47 }; 48 49 apbclk: apbclk { 50 compatible = "fixed-clock"; 51 clock-frequency = <50000000>; 52 #clock-cells = <0>; 53 }; 54 55 mmcclk: mmcclk { 56 compatible = "fixed-clock"; 57 /* 58 * DW sdio controller has external ciu clock divider 59 * controlled via register in SDIO IP. It divides 60 * sdio_ref_clk (which comes from CGU) by 16 for 61 * default. So default mmcclk clock (which comes 62 * to sdk_in) is 25000000 Hz. 63 */ 64 clock-frequency = <25000000>; 65 #clock-cells = <0>; 66 }; 67 68 pguclk: pguclk { 69 #clock-cells = <0>; 70 compatible = "fixed-clock"; 71 clock-frequency = <74250000>; 72 }; 73 }; 74 75 gmac: ethernet@18000 { 76 #interrupt-cells = <1>; 77 compatible = "snps,dwmac"; 78 reg = < 0x18000 0x2000 >; 79 interrupts = < 4 >; 80 interrupt-names = "macirq"; 81 phy-mode = "rgmii"; 82 snps,pbl = < 32 >; 83 clocks = <&apbclk>; 84 clock-names = "stmmaceth"; 85 max-speed = <100>; 86 resets = <&creg_rst 5>; 87 reset-names = "stmmaceth"; 88 mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */ 89 }; 90 91 ehci@40000 { 92 compatible = "generic-ehci"; 93 reg = < 0x40000 0x100 >; 94 interrupts = < 8 >; 95 }; 96 97 ohci@60000 { 98 compatible = "generic-ohci"; 99 reg = < 0x60000 0x100 >; 100 interrupts = < 8 >; 101 }; 102 103 /* 104 * According to DW Mobile Storage databook it is required 105 * to use "Hold Register" if card is enumerated in SDR12 or 106 * SDR25 modes. 107 * 108 * Utilization of "Hold Register" is already implemented via 109 * dw_mci_pltfm_prepare_command() which in its turn gets 110 * used through dw_mci_drv_data->prepare_command call-back. 111 * This call-back is used in Altera Socfpga platform and so 112 * we may reuse it saying that we're compatible with their 113 * "altr,socfpga-dw-mshc". 114 * 115 * Most probably "Hold Register" utilization is platform- 116 * independent requirement which means that single unified 117 * "snps,dw-mshc" should be enough for all users of DW MMC once 118 * dw_mci_pltfm_prepare_command() is used in generic platform 119 * code. 120 */ 121 mmc@15000 { 122 compatible = "altr,socfpga-dw-mshc"; 123 reg = < 0x15000 0x400 >; 124 fifo-depth = < 16 >; 125 card-detect-delay = < 200 >; 126 clocks = <&apbclk>, <&mmcclk>; 127 clock-names = "biu", "ciu"; 128 interrupts = < 7 >; 129 bus-width = < 4 >; 130 }; 131 132 uart@20000 { 133 compatible = "snps,dw-apb-uart"; 134 reg = <0x20000 0x100>; 135 clock-frequency = <33333333>; 136 interrupts = <17>; 137 baud = <115200>; 138 reg-shift = <2>; 139 reg-io-width = <4>; 140 }; 141 142 uart@21000 { 143 compatible = "snps,dw-apb-uart"; 144 reg = <0x21000 0x100>; 145 clock-frequency = <33333333>; 146 interrupts = <18>; 147 baud = <115200>; 148 reg-shift = <2>; 149 reg-io-width = <4>; 150 }; 151 152 /* UART muxed with USB data port (ttyS3) */ 153 uart@22000 { 154 compatible = "snps,dw-apb-uart"; 155 reg = <0x22000 0x100>; 156 clock-frequency = <33333333>; 157 interrupts = <19>; 158 baud = <115200>; 159 reg-shift = <2>; 160 reg-io-width = <4>; 161 }; 162 163 i2c@1d000 { 164 compatible = "snps,designware-i2c"; 165 reg = <0x1d000 0x100>; 166 clock-frequency = <400000>; 167 clocks = <&i2cclk>; 168 interrupts = <14>; 169 }; 170 171 i2s: i2s@1e000 { 172 compatible = "snps,designware-i2s"; 173 reg = <0x1e000 0x100>; 174 clocks = <&i2sclk 0>; 175 clock-names = "i2sclk"; 176 interrupts = <15>; 177 #sound-dai-cells = <0>; 178 }; 179 180 i2c@1f000 { 181 compatible = "snps,designware-i2c"; 182 #address-cells = <1>; 183 #size-cells = <0>; 184 reg = <0x1f000 0x100>; 185 clock-frequency = <400000>; 186 clocks = <&i2cclk>; 187 interrupts = <16>; 188 189 adv7511:adv7511@39{ 190 compatible="adi,adv7511"; 191 reg = <0x39>; 192 interrupts = <23>; 193 adi,input-depth = <8>; 194 adi,input-colorspace = "rgb"; 195 adi,input-clock = "1x"; 196 adi,clock-delay = <0x03>; 197 #sound-dai-cells = <0>; 198 199 ports { 200 #address-cells = <1>; 201 #size-cells = <0>; 202 203 /* RGB/YUV input */ 204 port@0 { 205 reg = <0>; 206 adv7511_input:endpoint { 207 remote-endpoint = <&pgu_output>; 208 }; 209 }; 210 211 /* HDMI output */ 212 port@1 { 213 reg = <1>; 214 adv7511_output: endpoint { 215 remote-endpoint = <&hdmi_connector_in>; 216 }; 217 }; 218 }; 219 }; 220 221 eeprom@54{ 222 compatible = "atmel,24c01"; 223 reg = <0x54>; 224 pagesize = <0x8>; 225 }; 226 227 eeprom@57{ 228 compatible = "atmel,24c04"; 229 reg = <0x57>; 230 pagesize = <0x8>; 231 }; 232 }; 233 234 hdmi0: connector { 235 compatible = "hdmi-connector"; 236 type = "a"; 237 port { 238 hdmi_connector_in: endpoint { 239 remote-endpoint = <&adv7511_output>; 240 }; 241 }; 242 }; 243 244 gpio0:gpio@13000 { 245 compatible = "snps,dw-apb-gpio"; 246 reg = <0x13000 0x1000>; 247 #address-cells = <1>; 248 #size-cells = <0>; 249 250 gpio0_banka: gpio-controller@0 { 251 compatible = "snps,dw-apb-gpio-port"; 252 gpio-controller; 253 #gpio-cells = <2>; 254 snps,nr-gpios = <32>; 255 reg = <0>; 256 }; 257 258 gpio0_bankb: gpio-controller@1 { 259 compatible = "snps,dw-apb-gpio-port"; 260 gpio-controller; 261 #gpio-cells = <2>; 262 snps,nr-gpios = <8>; 263 reg = <1>; 264 }; 265 266 gpio0_bankc: gpio-controller@2 { 267 compatible = "snps,dw-apb-gpio-port"; 268 gpio-controller; 269 #gpio-cells = <2>; 270 snps,nr-gpios = <8>; 271 reg = <2>; 272 }; 273 }; 274 275 gpio1:gpio@14000 { 276 compatible = "snps,dw-apb-gpio"; 277 reg = <0x14000 0x1000>; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 281 gpio1_banka: gpio-controller@0 { 282 compatible = "snps,dw-apb-gpio-port"; 283 gpio-controller; 284 #gpio-cells = <2>; 285 snps,nr-gpios = <30>; 286 reg = <0>; 287 }; 288 289 gpio1_bankb: gpio-controller@1 { 290 compatible = "snps,dw-apb-gpio-port"; 291 gpio-controller; 292 #gpio-cells = <2>; 293 snps,nr-gpios = <10>; 294 reg = <1>; 295 }; 296 297 gpio1_bankc: gpio-controller@2 { 298 compatible = "snps,dw-apb-gpio-port"; 299 gpio-controller; 300 #gpio-cells = <2>; 301 snps,nr-gpios = <8>; 302 reg = <2>; 303 }; 304 }; 305 306 pgu@17000 { 307 compatible = "snps,arcpgu"; 308 reg = <0x17000 0x400>; 309 encoder-slave = <&adv7511>; 310 clocks = <&pguclk>; 311 clock-names = "pxlclk"; 312 memory-region = <&frame_buffer>; 313 port { 314 pgu_output: endpoint { 315 remote-endpoint = <&adv7511_input>; 316 }; 317 }; 318 }; 319 320 sound_playback { 321 compatible = "simple-audio-card"; 322 simple-audio-card,name = "AXS10x HDMI Audio"; 323 simple-audio-card,format = "i2s"; 324 simple-audio-card,cpu { 325 sound-dai = <&i2s>; 326 }; 327 simple-audio-card,codec { 328 sound-dai = <&adv7511>; 329 }; 330 }; 331 }; 332}; 333