1/* 2 * Support for peripherals on the AXS10x mainboard 3 * 4 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11/ { 12 axs10x_mb { 13 compatible = "simple-bus"; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 ranges = <0x00000000 0xe0000000 0x10000000>; 17 interrupt-parent = <&mb_intc>; 18 19 clocks { 20 i2cclk: i2cclk { 21 compatible = "fixed-clock"; 22 clock-frequency = <50000000>; 23 #clock-cells = <0>; 24 }; 25 26 apbclk: apbclk { 27 compatible = "fixed-clock"; 28 clock-frequency = <50000000>; 29 #clock-cells = <0>; 30 }; 31 32 mmcclk: mmcclk { 33 compatible = "fixed-clock"; 34 clock-frequency = <50000000>; 35 #clock-cells = <0>; 36 }; 37 }; 38 39 ethernet@0x18000 { 40 #interrupt-cells = <1>; 41 compatible = "snps,dwmac"; 42 reg = < 0x18000 0x2000 >; 43 interrupts = < 4 >; 44 interrupt-names = "macirq"; 45 phy-mode = "rgmii"; 46 snps,pbl = < 32 >; 47 clocks = <&apbclk>; 48 clock-names = "stmmaceth"; 49 }; 50 51 ehci@0x40000 { 52 compatible = "generic-ehci"; 53 reg = < 0x40000 0x100 >; 54 interrupts = < 8 >; 55 }; 56 57 ohci@0x60000 { 58 compatible = "generic-ohci"; 59 reg = < 0x60000 0x100 >; 60 interrupts = < 8 >; 61 }; 62 63 /* 64 * According to DW Mobile Storage databook it is required 65 * to use "Hold Register" if card is enumerated in SDR12 or 66 * SDR25 modes. 67 * 68 * Utilization of "Hold Register" is already implemented via 69 * dw_mci_pltfm_prepare_command() which in its turn gets 70 * used through dw_mci_drv_data->prepare_command call-back. 71 * This call-back is used in Altera Socfpga platform and so 72 * we may reuse it saying that we're compatible with their 73 * "altr,socfpga-dw-mshc". 74 * 75 * Most probably "Hold Register" utilization is platform- 76 * independent requirement which means that single unified 77 * "snps,dw-mshc" should be enough for all users of DW MMC once 78 * dw_mci_pltfm_prepare_command() is used in generic platform 79 * code. 80 */ 81 mmc@0x15000 { 82 compatible = "altr,socfpga-dw-mshc"; 83 reg = < 0x15000 0x400 >; 84 num-slots = < 1 >; 85 fifo-depth = < 16 >; 86 card-detect-delay = < 200 >; 87 clocks = <&apbclk>, <&mmcclk>; 88 clock-names = "biu", "ciu"; 89 interrupts = < 7 >; 90 bus-width = < 4 >; 91 }; 92 93 uart@0x20000 { 94 compatible = "snps,dw-apb-uart"; 95 reg = <0x20000 0x100>; 96 clock-frequency = <33333333>; 97 interrupts = <17>; 98 baud = <115200>; 99 reg-shift = <2>; 100 reg-io-width = <4>; 101 }; 102 103 uart@0x21000 { 104 compatible = "snps,dw-apb-uart"; 105 reg = <0x21000 0x100>; 106 clock-frequency = <33333333>; 107 interrupts = <18>; 108 baud = <115200>; 109 reg-shift = <2>; 110 reg-io-width = <4>; 111 }; 112 113 /* UART muxed with USB data port (ttyS3) */ 114 uart@0x22000 { 115 compatible = "snps,dw-apb-uart"; 116 reg = <0x22000 0x100>; 117 clock-frequency = <33333333>; 118 interrupts = <19>; 119 baud = <115200>; 120 reg-shift = <2>; 121 reg-io-width = <4>; 122 }; 123 124 i2c@0x1d000 { 125 compatible = "snps,designware-i2c"; 126 reg = <0x1d000 0x100>; 127 clock-frequency = <400000>; 128 clocks = <&i2cclk>; 129 interrupts = <14>; 130 }; 131 132 i2c@0x1e000 { 133 compatible = "snps,designware-i2c"; 134 reg = <0x1e000 0x100>; 135 clock-frequency = <400000>; 136 clocks = <&i2cclk>; 137 interrupts = <15>; 138 }; 139 140 i2c@0x1f000 { 141 compatible = "snps,designware-i2c"; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 reg = <0x1f000 0x100>; 145 clock-frequency = <400000>; 146 clocks = <&i2cclk>; 147 interrupts = <16>; 148 149 eeprom@0x54{ 150 compatible = "24c01"; 151 reg = <0x54>; 152 pagesize = <0x8>; 153 }; 154 155 eeprom@0x57{ 156 compatible = "24c04"; 157 reg = <0x57>; 158 pagesize = <0x8>; 159 }; 160 }; 161 162 gpio0:gpio@13000 { 163 compatible = "snps,dw-apb-gpio"; 164 reg = <0x13000 0x1000>; 165 #address-cells = <1>; 166 #size-cells = <0>; 167 168 gpio0_banka: gpio-controller@0 { 169 compatible = "snps,dw-apb-gpio-port"; 170 gpio-controller; 171 #gpio-cells = <2>; 172 snps,nr-gpios = <32>; 173 reg = <0>; 174 }; 175 176 gpio0_bankb: gpio-controller@1 { 177 compatible = "snps,dw-apb-gpio-port"; 178 gpio-controller; 179 #gpio-cells = <2>; 180 snps,nr-gpios = <8>; 181 reg = <1>; 182 }; 183 184 gpio0_bankc: gpio-controller@2 { 185 compatible = "snps,dw-apb-gpio-port"; 186 gpio-controller; 187 #gpio-cells = <2>; 188 snps,nr-gpios = <8>; 189 reg = <2>; 190 }; 191 }; 192 193 gpio1:gpio@14000 { 194 compatible = "snps,dw-apb-gpio"; 195 reg = <0x14000 0x1000>; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 199 gpio1_banka: gpio-controller@0 { 200 compatible = "snps,dw-apb-gpio-port"; 201 gpio-controller; 202 #gpio-cells = <2>; 203 snps,nr-gpios = <30>; 204 reg = <0>; 205 }; 206 207 gpio1_bankb: gpio-controller@1 { 208 compatible = "snps,dw-apb-gpio-port"; 209 gpio-controller; 210 #gpio-cells = <2>; 211 snps,nr-gpios = <10>; 212 reg = <1>; 213 }; 214 215 gpio1_bankc: gpio-controller@2 { 216 compatible = "snps,dw-apb-gpio-port"; 217 gpio-controller; 218 #gpio-cells = <2>; 219 snps,nr-gpios = <8>; 220 reg = <2>; 221 }; 222 }; 223 }; 224}; 225