1/* 2 * Support for peripherals on the AXS10x mainboard 3 * 4 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11/ { 12 axs10x_mb { 13 compatible = "simple-bus"; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 ranges = <0x00000000 0x0 0xe0000000 0x10000000>; 17 interrupt-parent = <&mb_intc>; 18 19 i2sclk: i2sclk@100a0 { 20 compatible = "snps,axs10x-i2s-pll-clock"; 21 reg = <0x100a0 0x10>; 22 clocks = <&i2spll_clk>; 23 #clock-cells = <0>; 24 }; 25 26 clocks { 27 i2spll_clk: i2spll_clk { 28 compatible = "fixed-clock"; 29 clock-frequency = <27000000>; 30 #clock-cells = <0>; 31 }; 32 33 i2cclk: i2cclk { 34 compatible = "fixed-clock"; 35 clock-frequency = <50000000>; 36 #clock-cells = <0>; 37 }; 38 39 apbclk: apbclk { 40 compatible = "fixed-clock"; 41 clock-frequency = <50000000>; 42 #clock-cells = <0>; 43 }; 44 45 mmcclk: mmcclk { 46 compatible = "fixed-clock"; 47 clock-frequency = <50000000>; 48 #clock-cells = <0>; 49 }; 50 51 pguclk: pguclk { 52 #clock-cells = <0>; 53 compatible = "fixed-clock"; 54 clock-frequency = <74250000>; 55 }; 56 }; 57 58 ethernet@0x18000 { 59 #interrupt-cells = <1>; 60 compatible = "snps,dwmac"; 61 reg = < 0x18000 0x2000 >; 62 interrupts = < 4 >; 63 interrupt-names = "macirq"; 64 phy-mode = "rgmii"; 65 snps,pbl = < 32 >; 66 clocks = <&apbclk>; 67 clock-names = "stmmaceth"; 68 max-speed = <100>; 69 }; 70 71 ehci@0x40000 { 72 compatible = "generic-ehci"; 73 reg = < 0x40000 0x100 >; 74 interrupts = < 8 >; 75 }; 76 77 ohci@0x60000 { 78 compatible = "generic-ohci"; 79 reg = < 0x60000 0x100 >; 80 interrupts = < 8 >; 81 }; 82 83 /* 84 * According to DW Mobile Storage databook it is required 85 * to use "Hold Register" if card is enumerated in SDR12 or 86 * SDR25 modes. 87 * 88 * Utilization of "Hold Register" is already implemented via 89 * dw_mci_pltfm_prepare_command() which in its turn gets 90 * used through dw_mci_drv_data->prepare_command call-back. 91 * This call-back is used in Altera Socfpga platform and so 92 * we may reuse it saying that we're compatible with their 93 * "altr,socfpga-dw-mshc". 94 * 95 * Most probably "Hold Register" utilization is platform- 96 * independent requirement which means that single unified 97 * "snps,dw-mshc" should be enough for all users of DW MMC once 98 * dw_mci_pltfm_prepare_command() is used in generic platform 99 * code. 100 */ 101 mmc@0x15000 { 102 compatible = "altr,socfpga-dw-mshc"; 103 reg = < 0x15000 0x400 >; 104 num-slots = < 1 >; 105 fifo-depth = < 16 >; 106 card-detect-delay = < 200 >; 107 clocks = <&apbclk>, <&mmcclk>; 108 clock-names = "biu", "ciu"; 109 interrupts = < 7 >; 110 bus-width = < 4 >; 111 }; 112 113 uart@0x20000 { 114 compatible = "snps,dw-apb-uart"; 115 reg = <0x20000 0x100>; 116 clock-frequency = <33333333>; 117 interrupts = <17>; 118 baud = <115200>; 119 reg-shift = <2>; 120 reg-io-width = <4>; 121 }; 122 123 uart@0x21000 { 124 compatible = "snps,dw-apb-uart"; 125 reg = <0x21000 0x100>; 126 clock-frequency = <33333333>; 127 interrupts = <18>; 128 baud = <115200>; 129 reg-shift = <2>; 130 reg-io-width = <4>; 131 }; 132 133 /* UART muxed with USB data port (ttyS3) */ 134 uart@0x22000 { 135 compatible = "snps,dw-apb-uart"; 136 reg = <0x22000 0x100>; 137 clock-frequency = <33333333>; 138 interrupts = <19>; 139 baud = <115200>; 140 reg-shift = <2>; 141 reg-io-width = <4>; 142 }; 143 144 i2c@0x1d000 { 145 compatible = "snps,designware-i2c"; 146 reg = <0x1d000 0x100>; 147 clock-frequency = <400000>; 148 clocks = <&i2cclk>; 149 interrupts = <14>; 150 }; 151 152 i2s: i2s@1e000 { 153 compatible = "snps,designware-i2s"; 154 reg = <0x1e000 0x100>; 155 clocks = <&i2sclk 0>; 156 clock-names = "i2sclk"; 157 interrupts = <15>; 158 #sound-dai-cells = <0>; 159 }; 160 161 i2c@0x1f000 { 162 compatible = "snps,designware-i2c"; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 reg = <0x1f000 0x100>; 166 clock-frequency = <400000>; 167 clocks = <&i2cclk>; 168 interrupts = <16>; 169 170 adv7511:adv7511@39{ 171 compatible="adi,adv7511"; 172 reg = <0x39>; 173 interrupts = <23>; 174 adi,input-depth = <8>; 175 adi,input-colorspace = "rgb"; 176 adi,input-clock = "1x"; 177 adi,clock-delay = <0x03>; 178 #sound-dai-cells = <0>; 179 180 ports { 181 #address-cells = <1>; 182 #size-cells = <0>; 183 184 /* RGB/YUV input */ 185 port@0 { 186 reg = <0>; 187 adv7511_input:endpoint { 188 remote-endpoint = <&pgu_output>; 189 }; 190 }; 191 192 /* HDMI output */ 193 port@1 { 194 reg = <1>; 195 adv7511_output: endpoint { 196 remote-endpoint = <&hdmi_connector_in>; 197 }; 198 }; 199 }; 200 }; 201 202 eeprom@0x54{ 203 compatible = "24c01"; 204 reg = <0x54>; 205 pagesize = <0x8>; 206 }; 207 208 eeprom@0x57{ 209 compatible = "24c04"; 210 reg = <0x57>; 211 pagesize = <0x8>; 212 }; 213 }; 214 215 hdmi0: connector { 216 compatible = "hdmi-connector"; 217 type = "a"; 218 port { 219 hdmi_connector_in: endpoint { 220 remote-endpoint = <&adv7511_output>; 221 }; 222 }; 223 }; 224 225 gpio0:gpio@13000 { 226 compatible = "snps,dw-apb-gpio"; 227 reg = <0x13000 0x1000>; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 231 gpio0_banka: gpio-controller@0 { 232 compatible = "snps,dw-apb-gpio-port"; 233 gpio-controller; 234 #gpio-cells = <2>; 235 snps,nr-gpios = <32>; 236 reg = <0>; 237 }; 238 239 gpio0_bankb: gpio-controller@1 { 240 compatible = "snps,dw-apb-gpio-port"; 241 gpio-controller; 242 #gpio-cells = <2>; 243 snps,nr-gpios = <8>; 244 reg = <1>; 245 }; 246 247 gpio0_bankc: gpio-controller@2 { 248 compatible = "snps,dw-apb-gpio-port"; 249 gpio-controller; 250 #gpio-cells = <2>; 251 snps,nr-gpios = <8>; 252 reg = <2>; 253 }; 254 }; 255 256 gpio1:gpio@14000 { 257 compatible = "snps,dw-apb-gpio"; 258 reg = <0x14000 0x1000>; 259 #address-cells = <1>; 260 #size-cells = <0>; 261 262 gpio1_banka: gpio-controller@0 { 263 compatible = "snps,dw-apb-gpio-port"; 264 gpio-controller; 265 #gpio-cells = <2>; 266 snps,nr-gpios = <30>; 267 reg = <0>; 268 }; 269 270 gpio1_bankb: gpio-controller@1 { 271 compatible = "snps,dw-apb-gpio-port"; 272 gpio-controller; 273 #gpio-cells = <2>; 274 snps,nr-gpios = <10>; 275 reg = <1>; 276 }; 277 278 gpio1_bankc: gpio-controller@2 { 279 compatible = "snps,dw-apb-gpio-port"; 280 gpio-controller; 281 #gpio-cells = <2>; 282 snps,nr-gpios = <8>; 283 reg = <2>; 284 }; 285 }; 286 287 pgu@17000 { 288 compatible = "snps,arcpgu"; 289 reg = <0x17000 0x400>; 290 encoder-slave = <&adv7511>; 291 clocks = <&pguclk>; 292 clock-names = "pxlclk"; 293 memory-region = <&frame_buffer>; 294 port { 295 pgu_output: endpoint { 296 remote-endpoint = <&adv7511_input>; 297 }; 298 }; 299 }; 300 301 sound_playback { 302 compatible = "simple-audio-card"; 303 simple-audio-card,name = "AXS10x HDMI Audio"; 304 simple-audio-card,format = "i2s"; 305 simple-audio-card,cpu { 306 sound-dai = <&i2s>; 307 }; 308 simple-audio-card,codec { 309 sound-dai = <&adv7511>; 310 }; 311 }; 312 }; 313}; 314