1# SPDX-License-Identifier: GPL-2.0-only 2# 3# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 4# 5 6config ARC 7 def_bool y 8 select ARC_TIMERS 9 select ARCH_HAS_DMA_COHERENT_TO_PFN 10 select ARCH_HAS_DMA_PREP_COHERENT 11 select ARCH_HAS_PTE_SPECIAL 12 select ARCH_HAS_SETUP_DMA_OPS 13 select ARCH_HAS_SYNC_DMA_FOR_CPU 14 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 15 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC 16 select ARCH_32BIT_OFF_T 17 select BUILDTIME_EXTABLE_SORT 18 select CLONE_BACKWARDS 19 select COMMON_CLK 20 select DMA_DIRECT_REMAP 21 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) 22 select GENERIC_CLOCKEVENTS 23 select GENERIC_FIND_FIRST_BIT 24 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP 25 select GENERIC_IRQ_SHOW 26 select GENERIC_PCI_IOMAP 27 select GENERIC_PENDING_IRQ if SMP 28 select GENERIC_SCHED_CLOCK 29 select GENERIC_SMP_IDLE_THREAD 30 select HAVE_ARCH_KGDB 31 select HAVE_ARCH_TRACEHOOK 32 select HAVE_DEBUG_STACKOVERFLOW 33 select HAVE_FUTEX_CMPXCHG if FUTEX 34 select HAVE_IOREMAP_PROT 35 select HAVE_KERNEL_GZIP 36 select HAVE_KERNEL_LZMA 37 select HAVE_KPROBES 38 select HAVE_KRETPROBES 39 select HAVE_MOD_ARCH_SPECIFIC 40 select HAVE_OPROFILE 41 select HAVE_PERF_EVENTS 42 select HANDLE_DOMAIN_IRQ 43 select IRQ_DOMAIN 44 select MODULES_USE_ELF_RELA 45 select OF 46 select OF_EARLY_FLATTREE 47 select PCI_SYSCALL if PCI 48 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING 49 50config ARCH_HAS_CACHE_LINE_SIZE 51 def_bool y 52 53config TRACE_IRQFLAGS_SUPPORT 54 def_bool y 55 56config LOCKDEP_SUPPORT 57 def_bool y 58 59config SCHED_OMIT_FRAME_POINTER 60 def_bool y 61 62config GENERIC_CSUM 63 def_bool y 64 65config ARCH_DISCONTIGMEM_ENABLE 66 def_bool n 67 68config ARCH_FLATMEM_ENABLE 69 def_bool y 70 71config MMU 72 def_bool y 73 74config NO_IOPORT_MAP 75 def_bool y 76 77config GENERIC_CALIBRATE_DELAY 78 def_bool y 79 80config GENERIC_HWEIGHT 81 def_bool y 82 83config STACKTRACE_SUPPORT 84 def_bool y 85 select STACKTRACE 86 87config HAVE_ARCH_TRANSPARENT_HUGEPAGE 88 def_bool y 89 depends on ARC_MMU_V4 90 91menu "ARC Architecture Configuration" 92 93menu "ARC Platform/SoC/Board" 94 95source "arch/arc/plat-tb10x/Kconfig" 96source "arch/arc/plat-axs10x/Kconfig" 97#New platform adds here 98source "arch/arc/plat-eznps/Kconfig" 99source "arch/arc/plat-hsdk/Kconfig" 100 101endmenu 102 103choice 104 prompt "ARC Instruction Set" 105 default ISA_ARCV2 106 107config ISA_ARCOMPACT 108 bool "ARCompact ISA" 109 select CPU_NO_EFFICIENT_FFS 110 help 111 The original ARC ISA of ARC600/700 cores 112 113config ISA_ARCV2 114 bool "ARC ISA v2" 115 select ARC_TIMERS_64BIT 116 help 117 ISA for the Next Generation ARC-HS cores 118 119endchoice 120 121menu "ARC CPU Configuration" 122 123choice 124 prompt "ARC Core" 125 default ARC_CPU_770 if ISA_ARCOMPACT 126 default ARC_CPU_HS if ISA_ARCV2 127 128if ISA_ARCOMPACT 129 130config ARC_CPU_750D 131 bool "ARC750D" 132 select ARC_CANT_LLSC 133 help 134 Support for ARC750 core 135 136config ARC_CPU_770 137 bool "ARC770" 138 select ARC_HAS_SWAPE 139 help 140 Support for ARC770 core introduced with Rel 4.10 (Summer 2011) 141 This core has a bunch of cool new features: 142 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) 143 Shared Address Spaces (for sharing TLB entries in MMU) 144 -Caches: New Prog Model, Region Flush 145 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr 146 147endif #ISA_ARCOMPACT 148 149config ARC_CPU_HS 150 bool "ARC-HS" 151 depends on ISA_ARCV2 152 help 153 Support for ARC HS38x Cores based on ARCv2 ISA 154 The notable features are: 155 - SMP configurations of upto 4 core with coherency 156 - Optional L2 Cache and IO-Coherency 157 - Revised Interrupt Architecture (multiple priorites, reg banks, 158 auto stack switch, auto regfile save/restore) 159 - MMUv4 (PIPT dcache, Huge Pages) 160 - Instructions for 161 * 64bit load/store: LDD, STD 162 * Hardware assisted divide/remainder: DIV, REM 163 * Function prologue/epilogue: ENTER_S, LEAVE_S 164 * IRQ enable/disable: CLRI, SETI 165 * pop count: FFS, FLS 166 * SETcc, BMSKN, XBFU... 167 168endchoice 169 170config CPU_BIG_ENDIAN 171 bool "Enable Big Endian Mode" 172 help 173 Build kernel for Big Endian Mode of ARC CPU 174 175config SMP 176 bool "Symmetric Multi-Processing" 177 select ARC_MCIP if ISA_ARCV2 178 help 179 This enables support for systems with more than one CPU. 180 181if SMP 182 183config NR_CPUS 184 int "Maximum number of CPUs (2-4096)" 185 range 2 4096 186 default "4" 187 188config ARC_SMP_HALT_ON_RESET 189 bool "Enable Halt-on-reset boot mode" 190 help 191 In SMP configuration cores can be configured as Halt-on-reset 192 or they could all start at same time. For Halt-on-reset, non 193 masters are parked until Master kicks them so they can start of 194 at designated entry point. For other case, all jump to common 195 entry point and spin wait for Master's signal. 196 197endif #SMP 198 199config ARC_MCIP 200 bool "ARConnect Multicore IP (MCIP) Support " 201 depends on ISA_ARCV2 202 default y if SMP 203 help 204 This IP block enables SMP in ARC-HS38 cores. 205 It provides for cross-core interrupts, multi-core debug 206 hardware semaphores, shared memory,.... 207 208menuconfig ARC_CACHE 209 bool "Enable Cache Support" 210 default y 211 212if ARC_CACHE 213 214config ARC_CACHE_LINE_SHIFT 215 int "Cache Line Length (as power of 2)" 216 range 5 7 217 default "6" 218 help 219 Starting with ARC700 4.9, Cache line length is configurable, 220 This option specifies "N", with Line-len = 2 power N 221 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively 222 Linux only supports same line lengths for I and D caches. 223 224config ARC_HAS_ICACHE 225 bool "Use Instruction Cache" 226 default y 227 228config ARC_HAS_DCACHE 229 bool "Use Data Cache" 230 default y 231 232config ARC_CACHE_PAGES 233 bool "Per Page Cache Control" 234 default y 235 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE 236 help 237 This can be used to over-ride the global I/D Cache Enable on a 238 per-page basis (but only for pages accessed via MMU such as 239 Kernel Virtual address or User Virtual Address) 240 TLB entries have a per-page Cache Enable Bit. 241 Note that Global I/D ENABLE + Per Page DISABLE works but corollary 242 Global DISABLE + Per Page ENABLE won't work 243 244config ARC_CACHE_VIPT_ALIASING 245 bool "Support VIPT Aliasing D$" 246 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT 247 248endif #ARC_CACHE 249 250config ARC_HAS_ICCM 251 bool "Use ICCM" 252 help 253 Single Cycle RAMS to store Fast Path Code 254 255config ARC_ICCM_SZ 256 int "ICCM Size in KB" 257 default "64" 258 depends on ARC_HAS_ICCM 259 260config ARC_HAS_DCCM 261 bool "Use DCCM" 262 help 263 Single Cycle RAMS to store Fast Path Data 264 265config ARC_DCCM_SZ 266 int "DCCM Size in KB" 267 default "64" 268 depends on ARC_HAS_DCCM 269 270config ARC_DCCM_BASE 271 hex "DCCM map address" 272 default "0xA0000000" 273 depends on ARC_HAS_DCCM 274 275choice 276 prompt "MMU Version" 277 default ARC_MMU_V3 if ARC_CPU_770 278 default ARC_MMU_V2 if ARC_CPU_750D 279 default ARC_MMU_V4 if ARC_CPU_HS 280 281if ISA_ARCOMPACT 282 283config ARC_MMU_V1 284 bool "MMU v1" 285 help 286 Orig ARC700 MMU 287 288config ARC_MMU_V2 289 bool "MMU v2" 290 help 291 Fixed the deficiency of v1 - possible thrashing in memcpy scenario 292 when 2 D-TLB and 1 I-TLB entries index into same 2way set. 293 294config ARC_MMU_V3 295 bool "MMU v3" 296 depends on ARC_CPU_770 297 help 298 Introduced with ARC700 4.10: New Features 299 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) 300 Shared Address Spaces (SASID) 301 302endif 303 304config ARC_MMU_V4 305 bool "MMU v4" 306 depends on ISA_ARCV2 307 308endchoice 309 310 311choice 312 prompt "MMU Page Size" 313 default ARC_PAGE_SIZE_8K 314 315config ARC_PAGE_SIZE_8K 316 bool "8KB" 317 help 318 Choose between 8k vs 16k 319 320config ARC_PAGE_SIZE_16K 321 bool "16KB" 322 depends on ARC_MMU_V3 || ARC_MMU_V4 323 324config ARC_PAGE_SIZE_4K 325 bool "4KB" 326 depends on ARC_MMU_V3 || ARC_MMU_V4 327 328endchoice 329 330choice 331 prompt "MMU Super Page Size" 332 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE 333 default ARC_HUGEPAGE_2M 334 335config ARC_HUGEPAGE_2M 336 bool "2MB" 337 338config ARC_HUGEPAGE_16M 339 bool "16MB" 340 341endchoice 342 343config NODES_SHIFT 344 int "Maximum NUMA Nodes (as a power of 2)" 345 default "0" if !DISCONTIGMEM 346 default "1" if DISCONTIGMEM 347 depends on NEED_MULTIPLE_NODES 348 ---help--- 349 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory 350 zones. 351 352if ISA_ARCOMPACT 353 354config ARC_COMPACT_IRQ_LEVELS 355 bool "Setup Timer IRQ as high Priority" 356 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy 357 depends on !SMP 358 359config ARC_FPU_SAVE_RESTORE 360 bool "Enable FPU state persistence across context switch" 361 help 362 Double Precision Floating Point unit had dedicated regs which 363 need to be saved/restored across context-switch. 364 Note that ARC FPU is overly simplistic, unlike say x86, which has 365 hardware pieces to allow software to conditionally save/restore, 366 based on actual usage of FPU by a task. Thus our implemn does 367 this for all tasks in system. 368 369endif #ISA_ARCOMPACT 370 371config ARC_CANT_LLSC 372 def_bool n 373 374config ARC_HAS_LLSC 375 bool "Insn: LLOCK/SCOND (efficient atomic ops)" 376 default y 377 depends on !ARC_CANT_LLSC 378 379config ARC_HAS_SWAPE 380 bool "Insn: SWAPE (endian-swap)" 381 default y 382 383if ISA_ARCV2 384 385config ARC_USE_UNALIGNED_MEM_ACCESS 386 bool "Enable unaligned access in HW" 387 default y 388 select HAVE_EFFICIENT_UNALIGNED_ACCESS 389 help 390 The ARC HS architecture supports unaligned memory access 391 which is disabled by default. Enable unaligned access in 392 hardware and use software to use it 393 394config ARC_HAS_LL64 395 bool "Insn: 64bit LDD/STD" 396 help 397 Enable gcc to generate 64-bit load/store instructions 398 ISA mandates even/odd registers to allow encoding of two 399 dest operands with 2 possible source operands. 400 default y 401 402config ARC_HAS_DIV_REM 403 bool "Insn: div, divu, rem, remu" 404 default y 405 406config ARC_HAS_ACCL_REGS 407 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)" 408 default y 409 help 410 Depending on the configuration, CPU can contain accumulator reg-pair 411 (also referred to as r58:r59). These can also be used by gcc as GPR so 412 kernel needs to save/restore per process 413 414config ARC_IRQ_NO_AUTOSAVE 415 bool "Disable hardware autosave regfile on interrupts" 416 default n 417 help 418 On HS cores, taken interrupt auto saves the regfile on stack. 419 This is programmable and can be optionally disabled in which case 420 software INTERRUPT_PROLOGUE/EPILGUE do the needed work 421 422endif # ISA_ARCV2 423 424endmenu # "ARC CPU Configuration" 425 426config LINUX_LINK_BASE 427 hex "Kernel link address" 428 default "0x80000000" 429 help 430 ARC700 divides the 32 bit phy address space into two equal halves 431 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU 432 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel 433 Typically Linux kernel is linked at the start of untransalted addr, 434 hence the default value of 0x8zs. 435 However some customers have peripherals mapped at this addr, so 436 Linux needs to be scooted a bit. 437 If you don't know what the above means, leave this setting alone. 438 This needs to match memory start address specified in Device Tree 439 440config LINUX_RAM_BASE 441 hex "RAM base address" 442 default LINUX_LINK_BASE 443 help 444 By default Linux is linked at base of RAM. However in some special 445 cases (such as HSDK), Linux can't be linked at start of DDR, hence 446 this option. 447 448config HIGHMEM 449 bool "High Memory Support" 450 select ARCH_DISCONTIGMEM_ENABLE 451 help 452 With ARC 2G:2G address split, only upper 2G is directly addressable by 453 kernel. Enable this to potentially allow access to rest of 2G and PAE 454 in future 455 456config ARC_HAS_PAE40 457 bool "Support for the 40-bit Physical Address Extension" 458 depends on ISA_ARCV2 459 select HIGHMEM 460 select PHYS_ADDR_T_64BIT 461 help 462 Enable access to physical memory beyond 4G, only supported on 463 ARC cores with 40 bit Physical Addressing support 464 465config ARC_KVADDR_SIZE 466 int "Kernel Virtual Address Space size (MB)" 467 range 0 512 468 default "256" 469 help 470 The kernel address space is carved out of 256MB of translated address 471 space for catering to vmalloc, modules, pkmap, fixmap. This however may 472 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow 473 this to be stretched to 512 MB (by extending into the reserved 474 kernel-user gutter) 475 476config ARC_CURR_IN_REG 477 bool "Dedicate Register r25 for current_task pointer" 478 default y 479 help 480 This reserved Register R25 to point to Current Task in 481 kernel mode. This saves memory access for each such access 482 483 484config ARC_EMUL_UNALIGNED 485 bool "Emulate unaligned memory access (userspace only)" 486 select SYSCTL_ARCH_UNALIGN_NO_WARN 487 select SYSCTL_ARCH_UNALIGN_ALLOW 488 depends on ISA_ARCOMPACT 489 help 490 This enables misaligned 16 & 32 bit memory access from user space. 491 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide 492 potential bugs in code 493 494config HZ 495 int "Timer Frequency" 496 default 100 497 498config ARC_METAWARE_HLINK 499 bool "Support for Metaware debugger assisted Host access" 500 help 501 This options allows a Linux userland apps to directly access 502 host file system (open/creat/read/write etc) with help from 503 Metaware Debugger. This can come in handy for Linux-host communication 504 when there is no real usable peripheral such as EMAC. 505 506menuconfig ARC_DBG 507 bool "ARC debugging" 508 default y 509 510if ARC_DBG 511 512config ARC_DW2_UNWIND 513 bool "Enable DWARF specific kernel stack unwind" 514 default y 515 select KALLSYMS 516 help 517 Compiles the kernel with DWARF unwind information and can be used 518 to get stack backtraces. 519 520 If you say Y here the resulting kernel image will be slightly larger 521 but not slower, and it will give very useful debugging information. 522 If you don't debug the kernel, you can say N, but we may not be able 523 to solve problems without frame unwind information 524 525config ARC_DBG_TLB_PARANOIA 526 bool "Paranoia Checks in Low Level TLB Handlers" 527 528endif 529 530config ARC_BUILTIN_DTB_NAME 531 string "Built in DTB" 532 help 533 Set the name of the DTB to embed in the vmlinux binary 534 Leaving it blank selects the minimal "skeleton" dtb 535 536endmenu # "ARC Architecture Configuration" 537 538config FORCE_MAX_ZONEORDER 539 int "Maximum zone order" 540 default "12" if ARC_HUGEPAGE_16M 541 default "11" 542 543source "kernel/power/Kconfig" 544