xref: /openbmc/linux/arch/arc/Kconfig (revision eb3fcf00) 
1#
2# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
3#
4# This program is free software; you can redistribute it and/or modify
5# it under the terms of the GNU General Public License version 2 as
6# published by the Free Software Foundation.
7#
8
9config ARC
10	def_bool y
11	select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
12	select BUILDTIME_EXTABLE_SORT
13	select COMMON_CLK
14	select CLONE_BACKWARDS
15	# ARC Busybox based initramfs absolutely relies on DEVTMPFS for /dev
16	select DEVTMPFS if !INITRAMFS_SOURCE=""
17	select GENERIC_ATOMIC64
18	select GENERIC_CLOCKEVENTS
19	select GENERIC_FIND_FIRST_BIT
20	# for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
21	select GENERIC_IRQ_SHOW
22	select GENERIC_PENDING_IRQ if SMP
23	select GENERIC_SMP_IDLE_THREAD
24	select HAVE_ARCH_KGDB
25	select HAVE_ARCH_TRACEHOOK
26	select HAVE_FUTEX_CMPXCHG
27	select HAVE_IOREMAP_PROT
28	select HAVE_KPROBES
29	select HAVE_KRETPROBES
30	select HAVE_MEMBLOCK
31	select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND
32	select HAVE_OPROFILE
33	select HAVE_PERF_EVENTS
34	select IRQ_DOMAIN
35	select MODULES_USE_ELF_RELA
36	select NO_BOOTMEM
37	select OF
38	select OF_EARLY_FLATTREE
39	select PERF_USE_VMALLOC
40	select HAVE_DEBUG_STACKOVERFLOW
41
42config TRACE_IRQFLAGS_SUPPORT
43	def_bool y
44
45config LOCKDEP_SUPPORT
46	def_bool y
47
48config SCHED_OMIT_FRAME_POINTER
49	def_bool y
50
51config GENERIC_CSUM
52	def_bool y
53
54config RWSEM_GENERIC_SPINLOCK
55	def_bool y
56
57config ARCH_FLATMEM_ENABLE
58	def_bool y
59
60config MMU
61	def_bool y
62
63config NO_IOPORT_MAP
64	def_bool y
65
66config GENERIC_CALIBRATE_DELAY
67	def_bool y
68
69config GENERIC_HWEIGHT
70	def_bool y
71
72config STACKTRACE_SUPPORT
73	def_bool y
74	select STACKTRACE
75
76config HAVE_LATENCYTOP_SUPPORT
77	def_bool y
78
79source "init/Kconfig"
80source "kernel/Kconfig.freezer"
81
82menu "ARC Architecture Configuration"
83
84menu "ARC Platform/SoC/Board"
85
86source "arch/arc/plat-sim/Kconfig"
87source "arch/arc/plat-tb10x/Kconfig"
88source "arch/arc/plat-axs10x/Kconfig"
89#New platform adds here
90
91endmenu
92
93choice
94	prompt "ARC Instruction Set"
95	default ISA_ARCOMPACT
96
97config ISA_ARCOMPACT
98	bool "ARCompact ISA"
99	help
100	  The original ARC ISA of ARC600/700 cores
101
102config ISA_ARCV2
103	bool "ARC ISA v2"
104	help
105	  ISA for the Next Generation ARC-HS cores
106
107endchoice
108
109menu "ARC CPU Configuration"
110
111choice
112	prompt "ARC Core"
113	default ARC_CPU_770 if ISA_ARCOMPACT
114	default ARC_CPU_HS if ISA_ARCV2
115
116if ISA_ARCOMPACT
117
118config ARC_CPU_750D
119	bool "ARC750D"
120	select ARC_CANT_LLSC
121	help
122	  Support for ARC750 core
123
124config ARC_CPU_770
125	bool "ARC770"
126	select ARC_HAS_SWAPE
127	help
128	  Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
129	  This core has a bunch of cool new features:
130	  -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
131                   Shared Address Spaces (for sharing TLB entires in MMU)
132	  -Caches: New Prog Model, Region Flush
133	  -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
134
135endif	#ISA_ARCOMPACT
136
137config ARC_CPU_HS
138	bool "ARC-HS"
139	depends on ISA_ARCV2
140	help
141	  Support for ARC HS38x Cores based on ARCv2 ISA
142	  The notable features are:
143	    - SMP configurations of upto 4 core with coherency
144	    - Optional L2 Cache and IO-Coherency
145	    - Revised Interrupt Architecture (multiple priorites, reg banks,
146	        auto stack switch, auto regfile save/restore)
147	    - MMUv4 (PIPT dcache, Huge Pages)
148	    - Instructions for
149		* 64bit load/store: LDD, STD
150		* Hardware assisted divide/remainder: DIV, REM
151		* Function prologue/epilogue: ENTER_S, LEAVE_S
152		* IRQ enable/disable: CLRI, SETI
153		* pop count: FFS, FLS
154		* SETcc, BMSKN, XBFU...
155
156endchoice
157
158config CPU_BIG_ENDIAN
159	bool "Enable Big Endian Mode"
160	default n
161	help
162	  Build kernel for Big Endian Mode of ARC CPU
163
164config SMP
165	bool "Symmetric Multi-Processing"
166	default n
167	select ARC_HAS_COH_CACHES if ISA_ARCV2
168	select ARC_MCIP if ISA_ARCV2
169	help
170	  This enables support for systems with more than one CPU.
171
172if SMP
173
174config ARC_HAS_COH_CACHES
175	def_bool n
176
177config ARC_HAS_REENTRANT_IRQ_LV2
178	def_bool n
179
180config ARC_MCIP
181	bool "ARConnect Multicore IP (MCIP) Support "
182	depends on ISA_ARCV2
183	help
184	  This IP block enables SMP in ARC-HS38 cores.
185	  It provides for cross-core interrupts, multi-core debug
186	  hardware semaphores, shared memory,....
187
188config NR_CPUS
189	int "Maximum number of CPUs (2-4096)"
190	range 2 4096
191	default "4"
192
193endif	#SMP
194
195menuconfig ARC_CACHE
196	bool "Enable Cache Support"
197	default y
198	# if SMP, cache enabled ONLY if ARC implementation has cache coherency
199	depends on !SMP || ARC_HAS_COH_CACHES
200
201if ARC_CACHE
202
203config ARC_CACHE_LINE_SHIFT
204	int "Cache Line Length (as power of 2)"
205	range 5 7
206	default "6"
207	help
208	  Starting with ARC700 4.9, Cache line length is configurable,
209	  This option specifies "N", with Line-len = 2 power N
210	  So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
211	  Linux only supports same line lengths for I and D caches.
212
213config ARC_HAS_ICACHE
214	bool "Use Instruction Cache"
215	default y
216
217config ARC_HAS_DCACHE
218	bool "Use Data Cache"
219	default y
220
221config ARC_CACHE_PAGES
222	bool "Per Page Cache Control"
223	default y
224	depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
225	help
226	  This can be used to over-ride the global I/D Cache Enable on a
227	  per-page basis (but only for pages accessed via MMU such as
228	  Kernel Virtual address or User Virtual Address)
229	  TLB entries have a per-page Cache Enable Bit.
230	  Note that Global I/D ENABLE + Per Page DISABLE works but corollary
231	  Global DISABLE + Per Page ENABLE won't work
232
233config ARC_CACHE_VIPT_ALIASING
234	bool "Support VIPT Aliasing D$"
235	depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
236	default n
237
238endif	#ARC_CACHE
239
240config ARC_HAS_ICCM
241	bool "Use ICCM"
242	help
243	  Single Cycle RAMS to store Fast Path Code
244	default n
245
246config ARC_ICCM_SZ
247	int "ICCM Size in KB"
248	default "64"
249	depends on ARC_HAS_ICCM
250
251config ARC_HAS_DCCM
252	bool "Use DCCM"
253	help
254	  Single Cycle RAMS to store Fast Path Data
255	default n
256
257config ARC_DCCM_SZ
258	int "DCCM Size in KB"
259	default "64"
260	depends on ARC_HAS_DCCM
261
262config ARC_DCCM_BASE
263	hex "DCCM map address"
264	default "0xA0000000"
265	depends on ARC_HAS_DCCM
266
267config ARC_HAS_HW_MPY
268	bool "Use Hardware Multiplier (Normal or Faster XMAC)"
269	default y
270	help
271	  Influences how gcc generates code for MPY operations.
272	  If enabled, MPYxx insns are generated, provided by Standard/XMAC
273	  Multipler. Otherwise software multipy lib is used
274
275choice
276	prompt "MMU Version"
277	default ARC_MMU_V3 if ARC_CPU_770
278	default ARC_MMU_V2 if ARC_CPU_750D
279	default ARC_MMU_V4 if ARC_CPU_HS
280
281config ARC_MMU_V1
282	bool "MMU v1"
283	help
284	  Orig ARC700 MMU
285
286config ARC_MMU_V2
287	bool "MMU v2"
288	help
289	  Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
290	  when 2 D-TLB and 1 I-TLB entries index into same 2way set.
291
292config ARC_MMU_V3
293	bool "MMU v3"
294	depends on ARC_CPU_770
295	help
296	  Introduced with ARC700 4.10: New Features
297	  Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
298	  Shared Address Spaces (SASID)
299
300config ARC_MMU_V4
301	bool "MMU v4"
302	depends on ISA_ARCV2
303
304endchoice
305
306
307choice
308	prompt "MMU Page Size"
309	default ARC_PAGE_SIZE_8K
310
311config ARC_PAGE_SIZE_8K
312	bool "8KB"
313	help
314	  Choose between 8k vs 16k
315
316config ARC_PAGE_SIZE_16K
317	bool "16KB"
318	depends on ARC_MMU_V3 || ARC_MMU_V4
319
320config ARC_PAGE_SIZE_4K
321	bool "4KB"
322	depends on ARC_MMU_V3 || ARC_MMU_V4
323
324endchoice
325
326if ISA_ARCOMPACT
327
328config ARC_COMPACT_IRQ_LEVELS
329	bool "ARCompact IRQ Priorities: High(2)/Low(1)"
330	default n
331	# Timer HAS to be high priority, for any other high priority config
332	select ARC_IRQ3_LV2
333	# if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
334	depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2
335
336if ARC_COMPACT_IRQ_LEVELS
337
338config ARC_IRQ3_LV2
339	bool
340
341config ARC_IRQ5_LV2
342	bool
343
344config ARC_IRQ6_LV2
345	bool
346
347endif	#ARC_COMPACT_IRQ_LEVELS
348
349config ARC_FPU_SAVE_RESTORE
350	bool "Enable FPU state persistence across context switch"
351	default n
352	help
353	  Double Precision Floating Point unit had dedictaed regs which
354	  need to be saved/restored across context-switch.
355	  Note that ARC FPU is overly simplistic, unlike say x86, which has
356	  hardware pieces to allow software to conditionally save/restore,
357	  based on actual usage of FPU by a task. Thus our implemn does
358	  this for all tasks in system.
359
360endif	#ISA_ARCOMPACT
361
362config ARC_CANT_LLSC
363	def_bool n
364
365config ARC_HAS_LLSC
366	bool "Insn: LLOCK/SCOND (efficient atomic ops)"
367	default y
368	depends on !ARC_CANT_LLSC
369
370config ARC_STAR_9000923308
371	bool "Workaround for llock/scond livelock"
372	default y
373	depends on ISA_ARCV2 && SMP && ARC_HAS_LLSC
374
375config ARC_HAS_SWAPE
376	bool "Insn: SWAPE (endian-swap)"
377	default y
378
379if ISA_ARCV2
380
381config ARC_HAS_LL64
382	bool "Insn: 64bit LDD/STD"
383	help
384	  Enable gcc to generate 64-bit load/store instructions
385	  ISA mandates even/odd registers to allow encoding of two
386	  dest operands with 2 possible source operands.
387	default y
388
389config ARC_HAS_DIV_REM
390	bool "Insn: div, divu, rem, remu"
391	default y
392
393config ARC_HAS_RTC
394	bool "Local 64-bit r/o cycle counter"
395	default n
396	depends on !SMP
397
398config ARC_HAS_GRTC
399	bool "SMP synchronized 64-bit cycle counter"
400	default y
401	depends on SMP
402
403config ARC_NUMBER_OF_INTERRUPTS
404	int "Number of interrupts"
405	range 8 240
406	default 32
407	help
408	  This defines the number of interrupts on the ARCv2HS core.
409	  It affects the size of vector table.
410	  The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable
411	  in hardware, it keep things simple for Linux to assume they are always
412	  present.
413
414endif	# ISA_ARCV2
415
416endmenu   # "ARC CPU Configuration"
417
418config LINUX_LINK_BASE
419	hex "Linux Link Address"
420	default "0x80000000"
421	help
422	  ARC700 divides the 32 bit phy address space into two equal halves
423	  -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
424	  -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
425	  Typically Linux kernel is linked at the start of untransalted addr,
426	  hence the default value of 0x8zs.
427	  However some customers have peripherals mapped at this addr, so
428	  Linux needs to be scooted a bit.
429	  If you don't know what the above means, leave this setting alone.
430
431config ARC_CURR_IN_REG
432	bool "Dedicate Register r25 for current_task pointer"
433	default y
434	help
435	  This reserved Register R25 to point to Current Task in
436	  kernel mode. This saves memory access for each such access
437
438
439config ARC_EMUL_UNALIGNED
440	bool "Emulate unaligned memory access (userspace only)"
441	default N
442	select SYSCTL_ARCH_UNALIGN_NO_WARN
443	select SYSCTL_ARCH_UNALIGN_ALLOW
444	depends on ISA_ARCOMPACT
445	help
446	  This enables misaligned 16 & 32 bit memory access from user space.
447	  Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
448	  potential bugs in code
449
450config HZ
451	int "Timer Frequency"
452	default 100
453
454config ARC_METAWARE_HLINK
455	bool "Support for Metaware debugger assisted Host access"
456	default n
457	help
458	  This options allows a Linux userland apps to directly access
459	  host file system (open/creat/read/write etc) with help from
460	  Metaware Debugger. This can come in handy for Linux-host communication
461	  when there is no real usable peripheral such as EMAC.
462
463menuconfig ARC_DBG
464	bool "ARC debugging"
465	default y
466
467if ARC_DBG
468
469config ARC_DW2_UNWIND
470	bool "Enable DWARF specific kernel stack unwind"
471	default y
472	select KALLSYMS
473	help
474	  Compiles the kernel with DWARF unwind information and can be used
475	  to get stack backtraces.
476
477	  If you say Y here the resulting kernel image will be slightly larger
478	  but not slower, and it will give very useful debugging information.
479	  If you don't debug the kernel, you can say N, but we may not be able
480	  to solve problems without frame unwind information
481
482config ARC_DBG_TLB_PARANOIA
483	bool "Paranoia Checks in Low Level TLB Handlers"
484	default n
485
486config ARC_DBG_TLB_MISS_COUNT
487	bool "Profile TLB Misses"
488	default n
489	select DEBUG_FS
490	help
491	  Counts number of I and D TLB Misses and exports them via Debugfs
492	  The counters can be cleared via Debugfs as well
493
494if SMP
495
496config ARC_IPI_DBG
497	bool "Debug Inter Core interrupts"
498	default n
499
500endif
501
502endif
503
504config ARC_UBOOT_SUPPORT
505	bool "Support uboot arg Handling"
506	default n
507	help
508	  ARC Linux by default checks for uboot provided args as pointers to
509	  external cmdline or DTB. This however breaks in absence of uboot,
510	  when booting from Metaware debugger directly, as the registers are
511	  not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
512	  registers look like uboot args to kernel which then chokes.
513	  So only enable the uboot arg checking/processing if users are sure
514	  of uboot being in play.
515
516config ARC_BUILTIN_DTB_NAME
517	string "Built in DTB"
518	help
519	  Set the name of the DTB to embed in the vmlinux binary
520	  Leaving it blank selects the minimal "skeleton" dtb
521
522source "kernel/Kconfig.preempt"
523
524menu "Executable file formats"
525source "fs/Kconfig.binfmt"
526endmenu
527
528endmenu	 # "ARC Architecture Configuration"
529
530source "mm/Kconfig"
531source "net/Kconfig"
532source "drivers/Kconfig"
533source "fs/Kconfig"
534source "arch/arc/Kconfig.debug"
535source "security/Kconfig"
536source "crypto/Kconfig"
537source "lib/Kconfig"
538source "kernel/power/Kconfig"
539