1# 2# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3# 4# This program is free software; you can redistribute it and/or modify 5# it under the terms of the GNU General Public License version 2 as 6# published by the Free Software Foundation. 7# 8 9config ARC 10 def_bool y 11 select ARC_TIMERS 12 select ARCH_HAS_SYNC_DMA_FOR_CPU 13 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 14 select ARCH_HAS_SG_CHAIN 15 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC 16 select BUILDTIME_EXTABLE_SORT 17 select CLONE_BACKWARDS 18 select COMMON_CLK 19 select DMA_NONCOHERENT_OPS 20 select DMA_NONCOHERENT_MMAP 21 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) 22 select GENERIC_CLOCKEVENTS 23 select GENERIC_FIND_FIRST_BIT 24 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP 25 select GENERIC_IRQ_SHOW 26 select GENERIC_PCI_IOMAP 27 select GENERIC_PENDING_IRQ if SMP 28 select GENERIC_SMP_IDLE_THREAD 29 select HAVE_ARCH_KGDB 30 select HAVE_ARCH_TRACEHOOK 31 select HAVE_FUTEX_CMPXCHG if FUTEX 32 select HAVE_IOREMAP_PROT 33 select HAVE_KPROBES 34 select HAVE_KRETPROBES 35 select HAVE_MEMBLOCK 36 select HAVE_MOD_ARCH_SPECIFIC 37 select HAVE_OPROFILE 38 select HAVE_PERF_EVENTS 39 select HANDLE_DOMAIN_IRQ 40 select IRQ_DOMAIN 41 select MODULES_USE_ELF_RELA 42 select NO_BOOTMEM 43 select OF 44 select OF_EARLY_FLATTREE 45 select OF_RESERVED_MEM 46 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING 47 select HAVE_DEBUG_STACKOVERFLOW 48 select HAVE_GENERIC_DMA_COHERENT 49 select HAVE_KERNEL_GZIP 50 select HAVE_KERNEL_LZMA 51 select ARCH_HAS_PTE_SPECIAL 52 53config ARCH_HAS_CACHE_LINE_SIZE 54 def_bool y 55 56config MIGHT_HAVE_PCI 57 bool 58 59config TRACE_IRQFLAGS_SUPPORT 60 def_bool y 61 62config LOCKDEP_SUPPORT 63 def_bool y 64 65config SCHED_OMIT_FRAME_POINTER 66 def_bool y 67 68config GENERIC_CSUM 69 def_bool y 70 71config RWSEM_GENERIC_SPINLOCK 72 def_bool y 73 74config ARCH_DISCONTIGMEM_ENABLE 75 def_bool n 76 77config ARCH_FLATMEM_ENABLE 78 def_bool y 79 80config MMU 81 def_bool y 82 83config NO_IOPORT_MAP 84 def_bool y 85 86config GENERIC_CALIBRATE_DELAY 87 def_bool y 88 89config GENERIC_HWEIGHT 90 def_bool y 91 92config STACKTRACE_SUPPORT 93 def_bool y 94 select STACKTRACE 95 96config HAVE_ARCH_TRANSPARENT_HUGEPAGE 97 def_bool y 98 depends on ARC_MMU_V4 99 100menu "ARC Architecture Configuration" 101 102menu "ARC Platform/SoC/Board" 103 104source "arch/arc/plat-tb10x/Kconfig" 105source "arch/arc/plat-axs10x/Kconfig" 106#New platform adds here 107source "arch/arc/plat-eznps/Kconfig" 108source "arch/arc/plat-hsdk/Kconfig" 109 110endmenu 111 112choice 113 prompt "ARC Instruction Set" 114 default ISA_ARCOMPACT 115 116config ISA_ARCOMPACT 117 bool "ARCompact ISA" 118 select CPU_NO_EFFICIENT_FFS 119 help 120 The original ARC ISA of ARC600/700 cores 121 122config ISA_ARCV2 123 bool "ARC ISA v2" 124 select ARC_TIMERS_64BIT 125 help 126 ISA for the Next Generation ARC-HS cores 127 128endchoice 129 130menu "ARC CPU Configuration" 131 132choice 133 prompt "ARC Core" 134 default ARC_CPU_770 if ISA_ARCOMPACT 135 default ARC_CPU_HS if ISA_ARCV2 136 137if ISA_ARCOMPACT 138 139config ARC_CPU_750D 140 bool "ARC750D" 141 select ARC_CANT_LLSC 142 help 143 Support for ARC750 core 144 145config ARC_CPU_770 146 bool "ARC770" 147 select ARC_HAS_SWAPE 148 help 149 Support for ARC770 core introduced with Rel 4.10 (Summer 2011) 150 This core has a bunch of cool new features: 151 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) 152 Shared Address Spaces (for sharing TLB entires in MMU) 153 -Caches: New Prog Model, Region Flush 154 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr 155 156endif #ISA_ARCOMPACT 157 158config ARC_CPU_HS 159 bool "ARC-HS" 160 depends on ISA_ARCV2 161 help 162 Support for ARC HS38x Cores based on ARCv2 ISA 163 The notable features are: 164 - SMP configurations of upto 4 core with coherency 165 - Optional L2 Cache and IO-Coherency 166 - Revised Interrupt Architecture (multiple priorites, reg banks, 167 auto stack switch, auto regfile save/restore) 168 - MMUv4 (PIPT dcache, Huge Pages) 169 - Instructions for 170 * 64bit load/store: LDD, STD 171 * Hardware assisted divide/remainder: DIV, REM 172 * Function prologue/epilogue: ENTER_S, LEAVE_S 173 * IRQ enable/disable: CLRI, SETI 174 * pop count: FFS, FLS 175 * SETcc, BMSKN, XBFU... 176 177endchoice 178 179config CPU_BIG_ENDIAN 180 bool "Enable Big Endian Mode" 181 default n 182 help 183 Build kernel for Big Endian Mode of ARC CPU 184 185config SMP 186 bool "Symmetric Multi-Processing" 187 default n 188 select ARC_MCIP if ISA_ARCV2 189 help 190 This enables support for systems with more than one CPU. 191 192if SMP 193 194config NR_CPUS 195 int "Maximum number of CPUs (2-4096)" 196 range 2 4096 197 default "4" 198 199config ARC_SMP_HALT_ON_RESET 200 bool "Enable Halt-on-reset boot mode" 201 default y if ARC_UBOOT_SUPPORT 202 help 203 In SMP configuration cores can be configured as Halt-on-reset 204 or they could all start at same time. For Halt-on-reset, non 205 masters are parked until Master kicks them so they can start of 206 at designated entry point. For other case, all jump to common 207 entry point and spin wait for Master's signal. 208 209endif #SMP 210 211config ARC_MCIP 212 bool "ARConnect Multicore IP (MCIP) Support " 213 depends on ISA_ARCV2 214 default y if SMP 215 help 216 This IP block enables SMP in ARC-HS38 cores. 217 It provides for cross-core interrupts, multi-core debug 218 hardware semaphores, shared memory,.... 219 220menuconfig ARC_CACHE 221 bool "Enable Cache Support" 222 default y 223 224if ARC_CACHE 225 226config ARC_CACHE_LINE_SHIFT 227 int "Cache Line Length (as power of 2)" 228 range 5 7 229 default "6" 230 help 231 Starting with ARC700 4.9, Cache line length is configurable, 232 This option specifies "N", with Line-len = 2 power N 233 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively 234 Linux only supports same line lengths for I and D caches. 235 236config ARC_HAS_ICACHE 237 bool "Use Instruction Cache" 238 default y 239 240config ARC_HAS_DCACHE 241 bool "Use Data Cache" 242 default y 243 244config ARC_CACHE_PAGES 245 bool "Per Page Cache Control" 246 default y 247 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE 248 help 249 This can be used to over-ride the global I/D Cache Enable on a 250 per-page basis (but only for pages accessed via MMU such as 251 Kernel Virtual address or User Virtual Address) 252 TLB entries have a per-page Cache Enable Bit. 253 Note that Global I/D ENABLE + Per Page DISABLE works but corollary 254 Global DISABLE + Per Page ENABLE won't work 255 256config ARC_CACHE_VIPT_ALIASING 257 bool "Support VIPT Aliasing D$" 258 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT 259 default n 260 261endif #ARC_CACHE 262 263config ARC_HAS_ICCM 264 bool "Use ICCM" 265 help 266 Single Cycle RAMS to store Fast Path Code 267 default n 268 269config ARC_ICCM_SZ 270 int "ICCM Size in KB" 271 default "64" 272 depends on ARC_HAS_ICCM 273 274config ARC_HAS_DCCM 275 bool "Use DCCM" 276 help 277 Single Cycle RAMS to store Fast Path Data 278 default n 279 280config ARC_DCCM_SZ 281 int "DCCM Size in KB" 282 default "64" 283 depends on ARC_HAS_DCCM 284 285config ARC_DCCM_BASE 286 hex "DCCM map address" 287 default "0xA0000000" 288 depends on ARC_HAS_DCCM 289 290choice 291 prompt "MMU Version" 292 default ARC_MMU_V3 if ARC_CPU_770 293 default ARC_MMU_V2 if ARC_CPU_750D 294 default ARC_MMU_V4 if ARC_CPU_HS 295 296if ISA_ARCOMPACT 297 298config ARC_MMU_V1 299 bool "MMU v1" 300 help 301 Orig ARC700 MMU 302 303config ARC_MMU_V2 304 bool "MMU v2" 305 help 306 Fixed the deficiency of v1 - possible thrashing in memcpy scenario 307 when 2 D-TLB and 1 I-TLB entries index into same 2way set. 308 309config ARC_MMU_V3 310 bool "MMU v3" 311 depends on ARC_CPU_770 312 help 313 Introduced with ARC700 4.10: New Features 314 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) 315 Shared Address Spaces (SASID) 316 317endif 318 319config ARC_MMU_V4 320 bool "MMU v4" 321 depends on ISA_ARCV2 322 323endchoice 324 325 326choice 327 prompt "MMU Page Size" 328 default ARC_PAGE_SIZE_8K 329 330config ARC_PAGE_SIZE_8K 331 bool "8KB" 332 help 333 Choose between 8k vs 16k 334 335config ARC_PAGE_SIZE_16K 336 bool "16KB" 337 depends on ARC_MMU_V3 || ARC_MMU_V4 338 339config ARC_PAGE_SIZE_4K 340 bool "4KB" 341 depends on ARC_MMU_V3 || ARC_MMU_V4 342 343endchoice 344 345choice 346 prompt "MMU Super Page Size" 347 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE 348 default ARC_HUGEPAGE_2M 349 350config ARC_HUGEPAGE_2M 351 bool "2MB" 352 353config ARC_HUGEPAGE_16M 354 bool "16MB" 355 356endchoice 357 358config NODES_SHIFT 359 int "Maximum NUMA Nodes (as a power of 2)" 360 default "0" if !DISCONTIGMEM 361 default "1" if DISCONTIGMEM 362 depends on NEED_MULTIPLE_NODES 363 ---help--- 364 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory 365 zones. 366 367if ISA_ARCOMPACT 368 369config ARC_COMPACT_IRQ_LEVELS 370 bool "Setup Timer IRQ as high Priority" 371 default n 372 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy 373 depends on !SMP 374 375config ARC_FPU_SAVE_RESTORE 376 bool "Enable FPU state persistence across context switch" 377 default n 378 help 379 Double Precision Floating Point unit had dedicated regs which 380 need to be saved/restored across context-switch. 381 Note that ARC FPU is overly simplistic, unlike say x86, which has 382 hardware pieces to allow software to conditionally save/restore, 383 based on actual usage of FPU by a task. Thus our implemn does 384 this for all tasks in system. 385 386endif #ISA_ARCOMPACT 387 388config ARC_CANT_LLSC 389 def_bool n 390 391config ARC_HAS_LLSC 392 bool "Insn: LLOCK/SCOND (efficient atomic ops)" 393 default y 394 depends on !ARC_CANT_LLSC 395 396config ARC_HAS_SWAPE 397 bool "Insn: SWAPE (endian-swap)" 398 default y 399 400if ISA_ARCV2 401 402config ARC_HAS_LL64 403 bool "Insn: 64bit LDD/STD" 404 help 405 Enable gcc to generate 64-bit load/store instructions 406 ISA mandates even/odd registers to allow encoding of two 407 dest operands with 2 possible source operands. 408 default y 409 410config ARC_HAS_DIV_REM 411 bool "Insn: div, divu, rem, remu" 412 default y 413 414config ARC_HAS_ACCL_REGS 415 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)" 416 default y 417 help 418 Depending on the configuration, CPU can contain accumulator reg-pair 419 (also referred to as r58:r59). These can also be used by gcc as GPR so 420 kernel needs to save/restore per process 421 422endif # ISA_ARCV2 423 424endmenu # "ARC CPU Configuration" 425 426config LINUX_LINK_BASE 427 hex "Kernel link address" 428 default "0x80000000" 429 help 430 ARC700 divides the 32 bit phy address space into two equal halves 431 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU 432 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel 433 Typically Linux kernel is linked at the start of untransalted addr, 434 hence the default value of 0x8zs. 435 However some customers have peripherals mapped at this addr, so 436 Linux needs to be scooted a bit. 437 If you don't know what the above means, leave this setting alone. 438 This needs to match memory start address specified in Device Tree 439 440config LINUX_RAM_BASE 441 hex "RAM base address" 442 default LINUX_LINK_BASE 443 help 444 By default Linux is linked at base of RAM. However in some special 445 cases (such as HSDK), Linux can't be linked at start of DDR, hence 446 this option. 447 448config HIGHMEM 449 bool "High Memory Support" 450 select ARCH_DISCONTIGMEM_ENABLE 451 help 452 With ARC 2G:2G address split, only upper 2G is directly addressable by 453 kernel. Enable this to potentially allow access to rest of 2G and PAE 454 in future 455 456config ARC_HAS_PAE40 457 bool "Support for the 40-bit Physical Address Extension" 458 default n 459 depends on ISA_ARCV2 460 select HIGHMEM 461 select PHYS_ADDR_T_64BIT 462 help 463 Enable access to physical memory beyond 4G, only supported on 464 ARC cores with 40 bit Physical Addressing support 465 466config ARC_KVADDR_SIZE 467 int "Kernel Virtual Address Space size (MB)" 468 range 0 512 469 default "256" 470 help 471 The kernel address space is carved out of 256MB of translated address 472 space for catering to vmalloc, modules, pkmap, fixmap. This however may 473 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow 474 this to be stretched to 512 MB (by extending into the reserved 475 kernel-user gutter) 476 477config ARC_CURR_IN_REG 478 bool "Dedicate Register r25 for current_task pointer" 479 default y 480 help 481 This reserved Register R25 to point to Current Task in 482 kernel mode. This saves memory access for each such access 483 484 485config ARC_EMUL_UNALIGNED 486 bool "Emulate unaligned memory access (userspace only)" 487 select SYSCTL_ARCH_UNALIGN_NO_WARN 488 select SYSCTL_ARCH_UNALIGN_ALLOW 489 depends on ISA_ARCOMPACT 490 help 491 This enables misaligned 16 & 32 bit memory access from user space. 492 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide 493 potential bugs in code 494 495config HZ 496 int "Timer Frequency" 497 default 100 498 499config ARC_METAWARE_HLINK 500 bool "Support for Metaware debugger assisted Host access" 501 default n 502 help 503 This options allows a Linux userland apps to directly access 504 host file system (open/creat/read/write etc) with help from 505 Metaware Debugger. This can come in handy for Linux-host communication 506 when there is no real usable peripheral such as EMAC. 507 508menuconfig ARC_DBG 509 bool "ARC debugging" 510 default y 511 512if ARC_DBG 513 514config ARC_DW2_UNWIND 515 bool "Enable DWARF specific kernel stack unwind" 516 default y 517 select KALLSYMS 518 help 519 Compiles the kernel with DWARF unwind information and can be used 520 to get stack backtraces. 521 522 If you say Y here the resulting kernel image will be slightly larger 523 but not slower, and it will give very useful debugging information. 524 If you don't debug the kernel, you can say N, but we may not be able 525 to solve problems without frame unwind information 526 527config ARC_DBG_TLB_PARANOIA 528 bool "Paranoia Checks in Low Level TLB Handlers" 529 default n 530 531endif 532 533config ARC_UBOOT_SUPPORT 534 bool "Support uboot arg Handling" 535 default n 536 help 537 ARC Linux by default checks for uboot provided args as pointers to 538 external cmdline or DTB. This however breaks in absence of uboot, 539 when booting from Metaware debugger directly, as the registers are 540 not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus 541 registers look like uboot args to kernel which then chokes. 542 So only enable the uboot arg checking/processing if users are sure 543 of uboot being in play. 544 545config ARC_BUILTIN_DTB_NAME 546 string "Built in DTB" 547 help 548 Set the name of the DTB to embed in the vmlinux binary 549 Leaving it blank selects the minimal "skeleton" dtb 550 551endmenu # "ARC Architecture Configuration" 552 553config FORCE_MAX_ZONEORDER 554 int "Maximum zone order" 555 default "12" if ARC_HUGEPAGE_16M 556 default "11" 557 558menu "Bus Support" 559 560config PCI 561 bool "PCI support" if MIGHT_HAVE_PCI 562 help 563 PCI is the name of a bus system, i.e., the way the CPU talks to 564 the other stuff inside your box. Find out if your board/platform 565 has PCI. 566 567 Note: PCIe support for Synopsys Device will be available only 568 when HAPS DX is configured with PCIe RC bitmap. If you have PCI, 569 say Y, otherwise N. 570 571config PCI_SYSCALL 572 def_bool PCI 573 574source "drivers/pci/Kconfig" 575 576endmenu 577 578source "kernel/power/Kconfig" 579