xref: /openbmc/linux/arch/arc/Kconfig (revision cc8bbe1a) 
1#
2# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
3#
4# This program is free software; you can redistribute it and/or modify
5# it under the terms of the GNU General Public License version 2 as
6# published by the Free Software Foundation.
7#
8
9config ARC
10	def_bool y
11	select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
12	select BUILDTIME_EXTABLE_SORT
13	select COMMON_CLK
14	select CLONE_BACKWARDS
15	# ARC Busybox based initramfs absolutely relies on DEVTMPFS for /dev
16	select DEVTMPFS if !INITRAMFS_SOURCE=""
17	select GENERIC_ATOMIC64
18	select GENERIC_CLOCKEVENTS
19	select GENERIC_FIND_FIRST_BIT
20	# for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
21	select GENERIC_IRQ_SHOW
22	select GENERIC_PENDING_IRQ if SMP
23	select GENERIC_SMP_IDLE_THREAD
24	select HAVE_ARCH_KGDB
25	select HAVE_ARCH_TRACEHOOK
26	select HAVE_FUTEX_CMPXCHG
27	select HAVE_IOREMAP_PROT
28	select HAVE_KPROBES
29	select HAVE_KRETPROBES
30	select HAVE_MEMBLOCK
31	select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND
32	select HAVE_OPROFILE
33	select HAVE_PERF_EVENTS
34	select IRQ_DOMAIN
35	select MODULES_USE_ELF_RELA
36	select NO_BOOTMEM
37	select OF
38	select OF_EARLY_FLATTREE
39	select PERF_USE_VMALLOC
40	select HAVE_DEBUG_STACKOVERFLOW
41
42config TRACE_IRQFLAGS_SUPPORT
43	def_bool y
44
45config LOCKDEP_SUPPORT
46	def_bool y
47
48config SCHED_OMIT_FRAME_POINTER
49	def_bool y
50
51config GENERIC_CSUM
52	def_bool y
53
54config RWSEM_GENERIC_SPINLOCK
55	def_bool y
56
57config ARCH_FLATMEM_ENABLE
58	def_bool y
59
60config MMU
61	def_bool y
62
63config NO_IOPORT_MAP
64	def_bool y
65
66config GENERIC_CALIBRATE_DELAY
67	def_bool y
68
69config GENERIC_HWEIGHT
70	def_bool y
71
72config STACKTRACE_SUPPORT
73	def_bool y
74	select STACKTRACE
75
76config HAVE_ARCH_TRANSPARENT_HUGEPAGE
77	def_bool y
78	depends on ARC_MMU_V4
79
80source "init/Kconfig"
81source "kernel/Kconfig.freezer"
82
83menu "ARC Architecture Configuration"
84
85menu "ARC Platform/SoC/Board"
86
87source "arch/arc/plat-sim/Kconfig"
88source "arch/arc/plat-tb10x/Kconfig"
89source "arch/arc/plat-axs10x/Kconfig"
90#New platform adds here
91
92endmenu
93
94choice
95	prompt "ARC Instruction Set"
96	default ISA_ARCOMPACT
97
98config ISA_ARCOMPACT
99	bool "ARCompact ISA"
100	help
101	  The original ARC ISA of ARC600/700 cores
102
103config ISA_ARCV2
104	bool "ARC ISA v2"
105	help
106	  ISA for the Next Generation ARC-HS cores
107
108endchoice
109
110menu "ARC CPU Configuration"
111
112choice
113	prompt "ARC Core"
114	default ARC_CPU_770 if ISA_ARCOMPACT
115	default ARC_CPU_HS if ISA_ARCV2
116
117if ISA_ARCOMPACT
118
119config ARC_CPU_750D
120	bool "ARC750D"
121	select ARC_CANT_LLSC
122	help
123	  Support for ARC750 core
124
125config ARC_CPU_770
126	bool "ARC770"
127	select ARC_HAS_SWAPE
128	help
129	  Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
130	  This core has a bunch of cool new features:
131	  -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
132                   Shared Address Spaces (for sharing TLB entires in MMU)
133	  -Caches: New Prog Model, Region Flush
134	  -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
135
136endif	#ISA_ARCOMPACT
137
138config ARC_CPU_HS
139	bool "ARC-HS"
140	depends on ISA_ARCV2
141	help
142	  Support for ARC HS38x Cores based on ARCv2 ISA
143	  The notable features are:
144	    - SMP configurations of upto 4 core with coherency
145	    - Optional L2 Cache and IO-Coherency
146	    - Revised Interrupt Architecture (multiple priorites, reg banks,
147	        auto stack switch, auto regfile save/restore)
148	    - MMUv4 (PIPT dcache, Huge Pages)
149	    - Instructions for
150		* 64bit load/store: LDD, STD
151		* Hardware assisted divide/remainder: DIV, REM
152		* Function prologue/epilogue: ENTER_S, LEAVE_S
153		* IRQ enable/disable: CLRI, SETI
154		* pop count: FFS, FLS
155		* SETcc, BMSKN, XBFU...
156
157endchoice
158
159config CPU_BIG_ENDIAN
160	bool "Enable Big Endian Mode"
161	default n
162	help
163	  Build kernel for Big Endian Mode of ARC CPU
164
165config SMP
166	bool "Symmetric Multi-Processing"
167	default n
168	select ARC_HAS_COH_CACHES if ISA_ARCV2
169	select ARC_MCIP if ISA_ARCV2
170	help
171	  This enables support for systems with more than one CPU.
172
173if SMP
174
175config ARC_HAS_COH_CACHES
176	def_bool n
177
178config ARC_HAS_REENTRANT_IRQ_LV2
179	def_bool n
180
181config ARC_MCIP
182	bool "ARConnect Multicore IP (MCIP) Support "
183	depends on ISA_ARCV2
184	help
185	  This IP block enables SMP in ARC-HS38 cores.
186	  It provides for cross-core interrupts, multi-core debug
187	  hardware semaphores, shared memory,....
188
189config NR_CPUS
190	int "Maximum number of CPUs (2-4096)"
191	range 2 4096
192	default "4"
193
194config ARC_SMP_HALT_ON_RESET
195	bool "Enable Halt-on-reset boot mode"
196	default y if ARC_UBOOT_SUPPORT
197	help
198	  In SMP configuration cores can be configured as Halt-on-reset
199	  or they could all start at same time. For Halt-on-reset, non
200	  masters are parked until Master kicks them so they can start of
201	  at designated entry point. For other case, all jump to common
202	  entry point and spin wait for Master's signal.
203
204endif	#SMP
205
206menuconfig ARC_CACHE
207	bool "Enable Cache Support"
208	default y
209	# if SMP, cache enabled ONLY if ARC implementation has cache coherency
210	depends on !SMP || ARC_HAS_COH_CACHES
211
212if ARC_CACHE
213
214config ARC_CACHE_LINE_SHIFT
215	int "Cache Line Length (as power of 2)"
216	range 5 7
217	default "6"
218	help
219	  Starting with ARC700 4.9, Cache line length is configurable,
220	  This option specifies "N", with Line-len = 2 power N
221	  So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
222	  Linux only supports same line lengths for I and D caches.
223
224config ARC_HAS_ICACHE
225	bool "Use Instruction Cache"
226	default y
227
228config ARC_HAS_DCACHE
229	bool "Use Data Cache"
230	default y
231
232config ARC_CACHE_PAGES
233	bool "Per Page Cache Control"
234	default y
235	depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
236	help
237	  This can be used to over-ride the global I/D Cache Enable on a
238	  per-page basis (but only for pages accessed via MMU such as
239	  Kernel Virtual address or User Virtual Address)
240	  TLB entries have a per-page Cache Enable Bit.
241	  Note that Global I/D ENABLE + Per Page DISABLE works but corollary
242	  Global DISABLE + Per Page ENABLE won't work
243
244config ARC_CACHE_VIPT_ALIASING
245	bool "Support VIPT Aliasing D$"
246	depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
247	default n
248
249endif	#ARC_CACHE
250
251config ARC_HAS_ICCM
252	bool "Use ICCM"
253	help
254	  Single Cycle RAMS to store Fast Path Code
255	default n
256
257config ARC_ICCM_SZ
258	int "ICCM Size in KB"
259	default "64"
260	depends on ARC_HAS_ICCM
261
262config ARC_HAS_DCCM
263	bool "Use DCCM"
264	help
265	  Single Cycle RAMS to store Fast Path Data
266	default n
267
268config ARC_DCCM_SZ
269	int "DCCM Size in KB"
270	default "64"
271	depends on ARC_HAS_DCCM
272
273config ARC_DCCM_BASE
274	hex "DCCM map address"
275	default "0xA0000000"
276	depends on ARC_HAS_DCCM
277
278config ARC_HAS_HW_MPY
279	bool "Use Hardware Multiplier (Normal or Faster XMAC)"
280	default y
281	help
282	  Influences how gcc generates code for MPY operations.
283	  If enabled, MPYxx insns are generated, provided by Standard/XMAC
284	  Multipler. Otherwise software multipy lib is used
285
286choice
287	prompt "MMU Version"
288	default ARC_MMU_V3 if ARC_CPU_770
289	default ARC_MMU_V2 if ARC_CPU_750D
290	default ARC_MMU_V4 if ARC_CPU_HS
291
292if ISA_ARCOMPACT
293
294config ARC_MMU_V1
295	bool "MMU v1"
296	help
297	  Orig ARC700 MMU
298
299config ARC_MMU_V2
300	bool "MMU v2"
301	help
302	  Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
303	  when 2 D-TLB and 1 I-TLB entries index into same 2way set.
304
305config ARC_MMU_V3
306	bool "MMU v3"
307	depends on ARC_CPU_770
308	help
309	  Introduced with ARC700 4.10: New Features
310	  Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
311	  Shared Address Spaces (SASID)
312
313endif
314
315config ARC_MMU_V4
316	bool "MMU v4"
317	depends on ISA_ARCV2
318
319endchoice
320
321
322choice
323	prompt "MMU Page Size"
324	default ARC_PAGE_SIZE_8K
325
326config ARC_PAGE_SIZE_8K
327	bool "8KB"
328	help
329	  Choose between 8k vs 16k
330
331config ARC_PAGE_SIZE_16K
332	bool "16KB"
333	depends on ARC_MMU_V3 || ARC_MMU_V4
334
335config ARC_PAGE_SIZE_4K
336	bool "4KB"
337	depends on ARC_MMU_V3 || ARC_MMU_V4
338
339endchoice
340
341choice
342	prompt "MMU Super Page Size"
343	depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
344	default ARC_HUGEPAGE_2M
345
346config ARC_HUGEPAGE_2M
347	bool "2MB"
348
349config ARC_HUGEPAGE_16M
350	bool "16MB"
351
352endchoice
353
354if ISA_ARCOMPACT
355
356config ARC_COMPACT_IRQ_LEVELS
357	bool "ARCompact IRQ Priorities: High(2)/Low(1)"
358	default n
359	# Timer HAS to be high priority, for any other high priority config
360	select ARC_IRQ3_LV2
361	# if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
362	depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2
363
364if ARC_COMPACT_IRQ_LEVELS
365
366config ARC_IRQ3_LV2
367	bool
368
369config ARC_IRQ5_LV2
370	bool
371
372config ARC_IRQ6_LV2
373	bool
374
375endif	#ARC_COMPACT_IRQ_LEVELS
376
377config ARC_FPU_SAVE_RESTORE
378	bool "Enable FPU state persistence across context switch"
379	default n
380	help
381	  Double Precision Floating Point unit had dedictaed regs which
382	  need to be saved/restored across context-switch.
383	  Note that ARC FPU is overly simplistic, unlike say x86, which has
384	  hardware pieces to allow software to conditionally save/restore,
385	  based on actual usage of FPU by a task. Thus our implemn does
386	  this for all tasks in system.
387
388endif	#ISA_ARCOMPACT
389
390config ARC_CANT_LLSC
391	def_bool n
392
393config ARC_HAS_LLSC
394	bool "Insn: LLOCK/SCOND (efficient atomic ops)"
395	default y
396	depends on !ARC_CANT_LLSC
397
398config ARC_STAR_9000923308
399	bool "Workaround for llock/scond livelock"
400	default y
401	depends on ISA_ARCV2 && SMP && ARC_HAS_LLSC
402
403config ARC_HAS_SWAPE
404	bool "Insn: SWAPE (endian-swap)"
405	default y
406
407if ISA_ARCV2
408
409config ARC_HAS_LL64
410	bool "Insn: 64bit LDD/STD"
411	help
412	  Enable gcc to generate 64-bit load/store instructions
413	  ISA mandates even/odd registers to allow encoding of two
414	  dest operands with 2 possible source operands.
415	default y
416
417config ARC_HAS_DIV_REM
418	bool "Insn: div, divu, rem, remu"
419	default y
420
421config ARC_HAS_RTC
422	bool "Local 64-bit r/o cycle counter"
423	default n
424	depends on !SMP
425
426config ARC_HAS_GFRC
427	bool "SMP synchronized 64-bit cycle counter"
428	default y
429	depends on SMP
430
431config ARC_NUMBER_OF_INTERRUPTS
432	int "Number of interrupts"
433	range 8 240
434	default 32
435	help
436	  This defines the number of interrupts on the ARCv2HS core.
437	  It affects the size of vector table.
438	  The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable
439	  in hardware, it keep things simple for Linux to assume they are always
440	  present.
441
442endif	# ISA_ARCV2
443
444endmenu   # "ARC CPU Configuration"
445
446config LINUX_LINK_BASE
447	hex "Linux Link Address"
448	default "0x80000000"
449	help
450	  ARC700 divides the 32 bit phy address space into two equal halves
451	  -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
452	  -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
453	  Typically Linux kernel is linked at the start of untransalted addr,
454	  hence the default value of 0x8zs.
455	  However some customers have peripherals mapped at this addr, so
456	  Linux needs to be scooted a bit.
457	  If you don't know what the above means, leave this setting alone.
458	  This needs to match memory start address specified in Device Tree
459
460config HIGHMEM
461	bool "High Memory Support"
462	help
463	  With ARC 2G:2G address split, only upper 2G is directly addressable by
464	  kernel. Enable this to potentially allow access to rest of 2G and PAE
465	  in future
466
467config ARC_HAS_PAE40
468	bool "Support for the 40-bit Physical Address Extension"
469	default n
470	depends on ISA_ARCV2
471	select HIGHMEM
472	help
473	  Enable access to physical memory beyond 4G, only supported on
474	  ARC cores with 40 bit Physical Addressing support
475
476config ARCH_PHYS_ADDR_T_64BIT
477	def_bool ARC_HAS_PAE40
478
479config ARCH_DMA_ADDR_T_64BIT
480	bool
481
482config ARC_CURR_IN_REG
483	bool "Dedicate Register r25 for current_task pointer"
484	default y
485	help
486	  This reserved Register R25 to point to Current Task in
487	  kernel mode. This saves memory access for each such access
488
489
490config ARC_EMUL_UNALIGNED
491	bool "Emulate unaligned memory access (userspace only)"
492	default N
493	select SYSCTL_ARCH_UNALIGN_NO_WARN
494	select SYSCTL_ARCH_UNALIGN_ALLOW
495	depends on ISA_ARCOMPACT
496	help
497	  This enables misaligned 16 & 32 bit memory access from user space.
498	  Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
499	  potential bugs in code
500
501config HZ
502	int "Timer Frequency"
503	default 100
504
505config ARC_METAWARE_HLINK
506	bool "Support for Metaware debugger assisted Host access"
507	default n
508	help
509	  This options allows a Linux userland apps to directly access
510	  host file system (open/creat/read/write etc) with help from
511	  Metaware Debugger. This can come in handy for Linux-host communication
512	  when there is no real usable peripheral such as EMAC.
513
514menuconfig ARC_DBG
515	bool "ARC debugging"
516	default y
517
518if ARC_DBG
519
520config ARC_DW2_UNWIND
521	bool "Enable DWARF specific kernel stack unwind"
522	default y
523	select KALLSYMS
524	help
525	  Compiles the kernel with DWARF unwind information and can be used
526	  to get stack backtraces.
527
528	  If you say Y here the resulting kernel image will be slightly larger
529	  but not slower, and it will give very useful debugging information.
530	  If you don't debug the kernel, you can say N, but we may not be able
531	  to solve problems without frame unwind information
532
533config ARC_DBG_TLB_PARANOIA
534	bool "Paranoia Checks in Low Level TLB Handlers"
535	default n
536
537config ARC_DBG_TLB_MISS_COUNT
538	bool "Profile TLB Misses"
539	default n
540	select DEBUG_FS
541	help
542	  Counts number of I and D TLB Misses and exports them via Debugfs
543	  The counters can be cleared via Debugfs as well
544
545if SMP
546
547config ARC_IPI_DBG
548	bool "Debug Inter Core interrupts"
549	default n
550
551endif
552
553endif
554
555config ARC_UBOOT_SUPPORT
556	bool "Support uboot arg Handling"
557	default n
558	help
559	  ARC Linux by default checks for uboot provided args as pointers to
560	  external cmdline or DTB. This however breaks in absence of uboot,
561	  when booting from Metaware debugger directly, as the registers are
562	  not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
563	  registers look like uboot args to kernel which then chokes.
564	  So only enable the uboot arg checking/processing if users are sure
565	  of uboot being in play.
566
567config ARC_BUILTIN_DTB_NAME
568	string "Built in DTB"
569	help
570	  Set the name of the DTB to embed in the vmlinux binary
571	  Leaving it blank selects the minimal "skeleton" dtb
572
573source "kernel/Kconfig.preempt"
574
575menu "Executable file formats"
576source "fs/Kconfig.binfmt"
577endmenu
578
579endmenu	 # "ARC Architecture Configuration"
580
581source "mm/Kconfig"
582
583config FORCE_MAX_ZONEORDER
584	int "Maximum zone order"
585	default "12" if ARC_HUGEPAGE_16M
586	default "11"
587
588source "net/Kconfig"
589source "drivers/Kconfig"
590source "fs/Kconfig"
591source "arch/arc/Kconfig.debug"
592source "security/Kconfig"
593source "crypto/Kconfig"
594source "lib/Kconfig"
595source "kernel/power/Kconfig"
596