xref: /openbmc/linux/arch/arc/Kconfig (revision 110e6f26) 
1#
2# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
3#
4# This program is free software; you can redistribute it and/or modify
5# it under the terms of the GNU General Public License version 2 as
6# published by the Free Software Foundation.
7#
8
9config ARC
10	def_bool y
11	select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
12	select BUILDTIME_EXTABLE_SORT
13	select COMMON_CLK
14	select CLONE_BACKWARDS
15	select GENERIC_ATOMIC64
16	select GENERIC_CLOCKEVENTS
17	select GENERIC_FIND_FIRST_BIT
18	# for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
19	select GENERIC_IRQ_SHOW
20	select GENERIC_PCI_IOMAP
21	select GENERIC_PENDING_IRQ if SMP
22	select GENERIC_SMP_IDLE_THREAD
23	select HAVE_ARCH_KGDB
24	select HAVE_ARCH_TRACEHOOK
25	select HAVE_FUTEX_CMPXCHG
26	select HAVE_IOREMAP_PROT
27	select HAVE_KPROBES
28	select HAVE_KRETPROBES
29	select HAVE_MEMBLOCK
30	select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND
31	select HAVE_OPROFILE
32	select HAVE_PERF_EVENTS
33	select IRQ_DOMAIN
34	select MODULES_USE_ELF_RELA
35	select NO_BOOTMEM
36	select OF
37	select OF_EARLY_FLATTREE
38	select PERF_USE_VMALLOC
39	select HAVE_DEBUG_STACKOVERFLOW
40
41config MIGHT_HAVE_PCI
42	bool
43
44config TRACE_IRQFLAGS_SUPPORT
45	def_bool y
46
47config LOCKDEP_SUPPORT
48	def_bool y
49
50config SCHED_OMIT_FRAME_POINTER
51	def_bool y
52
53config GENERIC_CSUM
54	def_bool y
55
56config RWSEM_GENERIC_SPINLOCK
57	def_bool y
58
59config ARCH_FLATMEM_ENABLE
60	def_bool y
61
62config MMU
63	def_bool y
64
65config NO_IOPORT_MAP
66	def_bool y
67
68config GENERIC_CALIBRATE_DELAY
69	def_bool y
70
71config GENERIC_HWEIGHT
72	def_bool y
73
74config STACKTRACE_SUPPORT
75	def_bool y
76	select STACKTRACE
77
78config HAVE_ARCH_TRANSPARENT_HUGEPAGE
79	def_bool y
80	depends on ARC_MMU_V4
81
82source "init/Kconfig"
83source "kernel/Kconfig.freezer"
84
85menu "ARC Architecture Configuration"
86
87menu "ARC Platform/SoC/Board"
88
89source "arch/arc/plat-sim/Kconfig"
90source "arch/arc/plat-tb10x/Kconfig"
91source "arch/arc/plat-axs10x/Kconfig"
92#New platform adds here
93
94endmenu
95
96choice
97	prompt "ARC Instruction Set"
98	default ISA_ARCOMPACT
99
100config ISA_ARCOMPACT
101	bool "ARCompact ISA"
102	help
103	  The original ARC ISA of ARC600/700 cores
104
105config ISA_ARCV2
106	bool "ARC ISA v2"
107	help
108	  ISA for the Next Generation ARC-HS cores
109
110endchoice
111
112menu "ARC CPU Configuration"
113
114choice
115	prompt "ARC Core"
116	default ARC_CPU_770 if ISA_ARCOMPACT
117	default ARC_CPU_HS if ISA_ARCV2
118
119if ISA_ARCOMPACT
120
121config ARC_CPU_750D
122	bool "ARC750D"
123	select ARC_CANT_LLSC
124	help
125	  Support for ARC750 core
126
127config ARC_CPU_770
128	bool "ARC770"
129	select ARC_HAS_SWAPE
130	help
131	  Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
132	  This core has a bunch of cool new features:
133	  -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
134                   Shared Address Spaces (for sharing TLB entires in MMU)
135	  -Caches: New Prog Model, Region Flush
136	  -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
137
138endif	#ISA_ARCOMPACT
139
140config ARC_CPU_HS
141	bool "ARC-HS"
142	depends on ISA_ARCV2
143	help
144	  Support for ARC HS38x Cores based on ARCv2 ISA
145	  The notable features are:
146	    - SMP configurations of upto 4 core with coherency
147	    - Optional L2 Cache and IO-Coherency
148	    - Revised Interrupt Architecture (multiple priorites, reg banks,
149	        auto stack switch, auto regfile save/restore)
150	    - MMUv4 (PIPT dcache, Huge Pages)
151	    - Instructions for
152		* 64bit load/store: LDD, STD
153		* Hardware assisted divide/remainder: DIV, REM
154		* Function prologue/epilogue: ENTER_S, LEAVE_S
155		* IRQ enable/disable: CLRI, SETI
156		* pop count: FFS, FLS
157		* SETcc, BMSKN, XBFU...
158
159endchoice
160
161config CPU_BIG_ENDIAN
162	bool "Enable Big Endian Mode"
163	default n
164	help
165	  Build kernel for Big Endian Mode of ARC CPU
166
167config SMP
168	bool "Symmetric Multi-Processing"
169	default n
170	select ARC_HAS_COH_CACHES if ISA_ARCV2
171	select ARC_MCIP if ISA_ARCV2
172	help
173	  This enables support for systems with more than one CPU.
174
175if SMP
176
177config ARC_HAS_COH_CACHES
178	def_bool n
179
180config ARC_HAS_REENTRANT_IRQ_LV2
181	def_bool n
182
183config ARC_MCIP
184	bool "ARConnect Multicore IP (MCIP) Support "
185	depends on ISA_ARCV2
186	help
187	  This IP block enables SMP in ARC-HS38 cores.
188	  It provides for cross-core interrupts, multi-core debug
189	  hardware semaphores, shared memory,....
190
191config NR_CPUS
192	int "Maximum number of CPUs (2-4096)"
193	range 2 4096
194	default "4"
195
196config ARC_SMP_HALT_ON_RESET
197	bool "Enable Halt-on-reset boot mode"
198	default y if ARC_UBOOT_SUPPORT
199	help
200	  In SMP configuration cores can be configured as Halt-on-reset
201	  or they could all start at same time. For Halt-on-reset, non
202	  masters are parked until Master kicks them so they can start of
203	  at designated entry point. For other case, all jump to common
204	  entry point and spin wait for Master's signal.
205
206endif	#SMP
207
208menuconfig ARC_CACHE
209	bool "Enable Cache Support"
210	default y
211	# if SMP, cache enabled ONLY if ARC implementation has cache coherency
212	depends on !SMP || ARC_HAS_COH_CACHES
213
214if ARC_CACHE
215
216config ARC_CACHE_LINE_SHIFT
217	int "Cache Line Length (as power of 2)"
218	range 5 7
219	default "6"
220	help
221	  Starting with ARC700 4.9, Cache line length is configurable,
222	  This option specifies "N", with Line-len = 2 power N
223	  So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
224	  Linux only supports same line lengths for I and D caches.
225
226config ARC_HAS_ICACHE
227	bool "Use Instruction Cache"
228	default y
229
230config ARC_HAS_DCACHE
231	bool "Use Data Cache"
232	default y
233
234config ARC_CACHE_PAGES
235	bool "Per Page Cache Control"
236	default y
237	depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
238	help
239	  This can be used to over-ride the global I/D Cache Enable on a
240	  per-page basis (but only for pages accessed via MMU such as
241	  Kernel Virtual address or User Virtual Address)
242	  TLB entries have a per-page Cache Enable Bit.
243	  Note that Global I/D ENABLE + Per Page DISABLE works but corollary
244	  Global DISABLE + Per Page ENABLE won't work
245
246config ARC_CACHE_VIPT_ALIASING
247	bool "Support VIPT Aliasing D$"
248	depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
249	default n
250
251endif	#ARC_CACHE
252
253config ARC_HAS_ICCM
254	bool "Use ICCM"
255	help
256	  Single Cycle RAMS to store Fast Path Code
257	default n
258
259config ARC_ICCM_SZ
260	int "ICCM Size in KB"
261	default "64"
262	depends on ARC_HAS_ICCM
263
264config ARC_HAS_DCCM
265	bool "Use DCCM"
266	help
267	  Single Cycle RAMS to store Fast Path Data
268	default n
269
270config ARC_DCCM_SZ
271	int "DCCM Size in KB"
272	default "64"
273	depends on ARC_HAS_DCCM
274
275config ARC_DCCM_BASE
276	hex "DCCM map address"
277	default "0xA0000000"
278	depends on ARC_HAS_DCCM
279
280choice
281	prompt "MMU Version"
282	default ARC_MMU_V3 if ARC_CPU_770
283	default ARC_MMU_V2 if ARC_CPU_750D
284	default ARC_MMU_V4 if ARC_CPU_HS
285
286if ISA_ARCOMPACT
287
288config ARC_MMU_V1
289	bool "MMU v1"
290	help
291	  Orig ARC700 MMU
292
293config ARC_MMU_V2
294	bool "MMU v2"
295	help
296	  Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
297	  when 2 D-TLB and 1 I-TLB entries index into same 2way set.
298
299config ARC_MMU_V3
300	bool "MMU v3"
301	depends on ARC_CPU_770
302	help
303	  Introduced with ARC700 4.10: New Features
304	  Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
305	  Shared Address Spaces (SASID)
306
307endif
308
309config ARC_MMU_V4
310	bool "MMU v4"
311	depends on ISA_ARCV2
312
313endchoice
314
315
316choice
317	prompt "MMU Page Size"
318	default ARC_PAGE_SIZE_8K
319
320config ARC_PAGE_SIZE_8K
321	bool "8KB"
322	help
323	  Choose between 8k vs 16k
324
325config ARC_PAGE_SIZE_16K
326	bool "16KB"
327	depends on ARC_MMU_V3 || ARC_MMU_V4
328
329config ARC_PAGE_SIZE_4K
330	bool "4KB"
331	depends on ARC_MMU_V3 || ARC_MMU_V4
332
333endchoice
334
335choice
336	prompt "MMU Super Page Size"
337	depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
338	default ARC_HUGEPAGE_2M
339
340config ARC_HUGEPAGE_2M
341	bool "2MB"
342
343config ARC_HUGEPAGE_16M
344	bool "16MB"
345
346endchoice
347
348if ISA_ARCOMPACT
349
350config ARC_COMPACT_IRQ_LEVELS
351	bool "ARCompact IRQ Priorities: High(2)/Low(1)"
352	default n
353	# Timer HAS to be high priority, for any other high priority config
354	select ARC_IRQ3_LV2
355	# if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
356	depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2
357
358if ARC_COMPACT_IRQ_LEVELS
359
360config ARC_IRQ3_LV2
361	bool
362
363config ARC_IRQ5_LV2
364	bool
365
366config ARC_IRQ6_LV2
367	bool
368
369endif	#ARC_COMPACT_IRQ_LEVELS
370
371config ARC_FPU_SAVE_RESTORE
372	bool "Enable FPU state persistence across context switch"
373	default n
374	help
375	  Double Precision Floating Point unit had dedictaed regs which
376	  need to be saved/restored across context-switch.
377	  Note that ARC FPU is overly simplistic, unlike say x86, which has
378	  hardware pieces to allow software to conditionally save/restore,
379	  based on actual usage of FPU by a task. Thus our implemn does
380	  this for all tasks in system.
381
382endif	#ISA_ARCOMPACT
383
384config ARC_CANT_LLSC
385	def_bool n
386
387config ARC_HAS_LLSC
388	bool "Insn: LLOCK/SCOND (efficient atomic ops)"
389	default y
390	depends on !ARC_CANT_LLSC
391
392config ARC_STAR_9000923308
393	bool "Workaround for llock/scond livelock"
394	default n
395	depends on ISA_ARCV2 && SMP && ARC_HAS_LLSC
396
397config ARC_HAS_SWAPE
398	bool "Insn: SWAPE (endian-swap)"
399	default y
400
401if ISA_ARCV2
402
403config ARC_HAS_LL64
404	bool "Insn: 64bit LDD/STD"
405	help
406	  Enable gcc to generate 64-bit load/store instructions
407	  ISA mandates even/odd registers to allow encoding of two
408	  dest operands with 2 possible source operands.
409	default y
410
411config ARC_HAS_DIV_REM
412	bool "Insn: div, divu, rem, remu"
413	default y
414
415config ARC_HAS_RTC
416	bool "Local 64-bit r/o cycle counter"
417	default n
418	depends on !SMP
419
420config ARC_HAS_GFRC
421	bool "SMP synchronized 64-bit cycle counter"
422	default y
423	depends on SMP
424
425config ARC_NUMBER_OF_INTERRUPTS
426	int "Number of interrupts"
427	range 8 240
428	default 32
429	help
430	  This defines the number of interrupts on the ARCv2HS core.
431	  It affects the size of vector table.
432	  The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable
433	  in hardware, it keep things simple for Linux to assume they are always
434	  present.
435
436endif	# ISA_ARCV2
437
438endmenu   # "ARC CPU Configuration"
439
440config LINUX_LINK_BASE
441	hex "Linux Link Address"
442	default "0x80000000"
443	help
444	  ARC700 divides the 32 bit phy address space into two equal halves
445	  -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
446	  -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
447	  Typically Linux kernel is linked at the start of untransalted addr,
448	  hence the default value of 0x8zs.
449	  However some customers have peripherals mapped at this addr, so
450	  Linux needs to be scooted a bit.
451	  If you don't know what the above means, leave this setting alone.
452	  This needs to match memory start address specified in Device Tree
453
454config HIGHMEM
455	bool "High Memory Support"
456	help
457	  With ARC 2G:2G address split, only upper 2G is directly addressable by
458	  kernel. Enable this to potentially allow access to rest of 2G and PAE
459	  in future
460
461config ARC_HAS_PAE40
462	bool "Support for the 40-bit Physical Address Extension"
463	default n
464	depends on ISA_ARCV2
465	help
466	  Enable access to physical memory beyond 4G, only supported on
467	  ARC cores with 40 bit Physical Addressing support
468
469config ARCH_PHYS_ADDR_T_64BIT
470	def_bool ARC_HAS_PAE40
471
472config ARCH_DMA_ADDR_T_64BIT
473	bool
474
475config ARC_PLAT_NEEDS_PHYS_TO_DMA
476	bool
477
478config ARC_CURR_IN_REG
479	bool "Dedicate Register r25 for current_task pointer"
480	default y
481	help
482	  This reserved Register R25 to point to Current Task in
483	  kernel mode. This saves memory access for each such access
484
485
486config ARC_EMUL_UNALIGNED
487	bool "Emulate unaligned memory access (userspace only)"
488	default N
489	select SYSCTL_ARCH_UNALIGN_NO_WARN
490	select SYSCTL_ARCH_UNALIGN_ALLOW
491	depends on ISA_ARCOMPACT
492	help
493	  This enables misaligned 16 & 32 bit memory access from user space.
494	  Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
495	  potential bugs in code
496
497config HZ
498	int "Timer Frequency"
499	default 100
500
501config ARC_METAWARE_HLINK
502	bool "Support for Metaware debugger assisted Host access"
503	default n
504	help
505	  This options allows a Linux userland apps to directly access
506	  host file system (open/creat/read/write etc) with help from
507	  Metaware Debugger. This can come in handy for Linux-host communication
508	  when there is no real usable peripheral such as EMAC.
509
510menuconfig ARC_DBG
511	bool "ARC debugging"
512	default y
513
514if ARC_DBG
515
516config ARC_DW2_UNWIND
517	bool "Enable DWARF specific kernel stack unwind"
518	default y
519	select KALLSYMS
520	help
521	  Compiles the kernel with DWARF unwind information and can be used
522	  to get stack backtraces.
523
524	  If you say Y here the resulting kernel image will be slightly larger
525	  but not slower, and it will give very useful debugging information.
526	  If you don't debug the kernel, you can say N, but we may not be able
527	  to solve problems without frame unwind information
528
529config ARC_DBG_TLB_PARANOIA
530	bool "Paranoia Checks in Low Level TLB Handlers"
531	default n
532
533config ARC_DBG_TLB_MISS_COUNT
534	bool "Profile TLB Misses"
535	default n
536	select DEBUG_FS
537	help
538	  Counts number of I and D TLB Misses and exports them via Debugfs
539	  The counters can be cleared via Debugfs as well
540
541endif
542
543config ARC_UBOOT_SUPPORT
544	bool "Support uboot arg Handling"
545	default n
546	help
547	  ARC Linux by default checks for uboot provided args as pointers to
548	  external cmdline or DTB. This however breaks in absence of uboot,
549	  when booting from Metaware debugger directly, as the registers are
550	  not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
551	  registers look like uboot args to kernel which then chokes.
552	  So only enable the uboot arg checking/processing if users are sure
553	  of uboot being in play.
554
555config ARC_BUILTIN_DTB_NAME
556	string "Built in DTB"
557	help
558	  Set the name of the DTB to embed in the vmlinux binary
559	  Leaving it blank selects the minimal "skeleton" dtb
560
561source "kernel/Kconfig.preempt"
562
563menu "Executable file formats"
564source "fs/Kconfig.binfmt"
565endmenu
566
567endmenu	 # "ARC Architecture Configuration"
568
569source "mm/Kconfig"
570
571config FORCE_MAX_ZONEORDER
572	int "Maximum zone order"
573	default "12" if ARC_HUGEPAGE_16M
574	default "11"
575
576source "net/Kconfig"
577source "drivers/Kconfig"
578
579menu "Bus Support"
580
581config PCI
582	bool "PCI support" if MIGHT_HAVE_PCI
583	help
584	  PCI is the name of a bus system, i.e., the way the CPU talks to
585	  the other stuff inside your box.  Find out if your board/platform
586	  has PCI.
587
588	  Note: PCIe support for Synopsys Device will be available only
589	  when HAPS DX is configured with PCIe RC bitmap. If you have PCI,
590	  say Y, otherwise N.
591
592config PCI_SYSCALL
593	def_bool PCI
594
595source "drivers/pci/Kconfig"
596source "drivers/pci/pcie/Kconfig"
597
598endmenu
599
600source "fs/Kconfig"
601source "arch/arc/Kconfig.debug"
602source "security/Kconfig"
603source "crypto/Kconfig"
604source "lib/Kconfig"
605source "kernel/power/Kconfig"
606