1 #include <linux/module.h> 2 #include <linux/types.h> 3 #include <linux/kernel.h> 4 #include <linux/sched.h> 5 #include <asm/ptrace.h> 6 7 #include <linux/uaccess.h> 8 9 #include "sfp-util.h" 10 #include <math-emu/soft-fp.h> 11 #include <math-emu/single.h> 12 #include <math-emu/double.h> 13 14 #define OPC_PAL 0x00 15 #define OPC_INTA 0x10 16 #define OPC_INTL 0x11 17 #define OPC_INTS 0x12 18 #define OPC_INTM 0x13 19 #define OPC_FLTC 0x14 20 #define OPC_FLTV 0x15 21 #define OPC_FLTI 0x16 22 #define OPC_FLTL 0x17 23 #define OPC_MISC 0x18 24 #define OPC_JSR 0x1a 25 26 #define FOP_SRC_S 0 27 #define FOP_SRC_T 2 28 #define FOP_SRC_Q 3 29 30 #define FOP_FNC_ADDx 0 31 #define FOP_FNC_CVTQL 0 32 #define FOP_FNC_SUBx 1 33 #define FOP_FNC_MULx 2 34 #define FOP_FNC_DIVx 3 35 #define FOP_FNC_CMPxUN 4 36 #define FOP_FNC_CMPxEQ 5 37 #define FOP_FNC_CMPxLT 6 38 #define FOP_FNC_CMPxLE 7 39 #define FOP_FNC_SQRTx 11 40 #define FOP_FNC_CVTxS 12 41 #define FOP_FNC_CVTxT 14 42 #define FOP_FNC_CVTxQ 15 43 44 #define MISC_TRAPB 0x0000 45 #define MISC_EXCB 0x0400 46 47 extern unsigned long alpha_read_fp_reg (unsigned long reg); 48 extern void alpha_write_fp_reg (unsigned long reg, unsigned long val); 49 extern unsigned long alpha_read_fp_reg_s (unsigned long reg); 50 extern void alpha_write_fp_reg_s (unsigned long reg, unsigned long val); 51 52 53 #ifdef MODULE 54 55 MODULE_DESCRIPTION("FP Software completion module"); 56 MODULE_LICENSE("GPL v2"); 57 58 extern long (*alpha_fp_emul_imprecise)(struct pt_regs *, unsigned long); 59 extern long (*alpha_fp_emul) (unsigned long pc); 60 61 static long (*save_emul_imprecise)(struct pt_regs *, unsigned long); 62 static long (*save_emul) (unsigned long pc); 63 64 long do_alpha_fp_emul_imprecise(struct pt_regs *, unsigned long); 65 long do_alpha_fp_emul(unsigned long); 66 67 int init_module(void) 68 { 69 save_emul_imprecise = alpha_fp_emul_imprecise; 70 save_emul = alpha_fp_emul; 71 alpha_fp_emul_imprecise = do_alpha_fp_emul_imprecise; 72 alpha_fp_emul = do_alpha_fp_emul; 73 return 0; 74 } 75 76 void cleanup_module(void) 77 { 78 alpha_fp_emul_imprecise = save_emul_imprecise; 79 alpha_fp_emul = save_emul; 80 } 81 82 #undef alpha_fp_emul_imprecise 83 #define alpha_fp_emul_imprecise do_alpha_fp_emul_imprecise 84 #undef alpha_fp_emul 85 #define alpha_fp_emul do_alpha_fp_emul 86 87 #endif /* MODULE */ 88 89 90 /* 91 * Emulate the floating point instruction at address PC. Returns -1 if the 92 * instruction to be emulated is illegal (such as with the opDEC trap), else 93 * the SI_CODE for a SIGFPE signal, else 0 if everything's ok. 94 * 95 * Notice that the kernel does not and cannot use FP regs. This is good 96 * because it means that instead of saving/restoring all fp regs, we simply 97 * stick the result of the operation into the appropriate register. 98 */ 99 long 100 alpha_fp_emul (unsigned long pc) 101 { 102 FP_DECL_EX; 103 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); 104 FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR); 105 106 unsigned long fa, fb, fc, func, mode, src; 107 unsigned long res, va, vb, vc, swcr, fpcr; 108 __u32 insn; 109 long si_code; 110 111 get_user(insn, (__u32 __user *)pc); 112 fc = (insn >> 0) & 0x1f; /* destination register */ 113 fb = (insn >> 16) & 0x1f; 114 fa = (insn >> 21) & 0x1f; 115 func = (insn >> 5) & 0xf; 116 src = (insn >> 9) & 0x3; 117 mode = (insn >> 11) & 0x3; 118 119 fpcr = rdfpcr(); 120 swcr = swcr_update_status(current_thread_info()->ieee_state, fpcr); 121 122 if (mode == 3) { 123 /* Dynamic -- get rounding mode from fpcr. */ 124 mode = (fpcr >> FPCR_DYN_SHIFT) & 3; 125 } 126 127 switch (src) { 128 case FOP_SRC_S: 129 va = alpha_read_fp_reg_s(fa); 130 vb = alpha_read_fp_reg_s(fb); 131 132 FP_UNPACK_SP(SA, &va); 133 FP_UNPACK_SP(SB, &vb); 134 135 switch (func) { 136 case FOP_FNC_SUBx: 137 FP_SUB_S(SR, SA, SB); 138 goto pack_s; 139 140 case FOP_FNC_ADDx: 141 FP_ADD_S(SR, SA, SB); 142 goto pack_s; 143 144 case FOP_FNC_MULx: 145 FP_MUL_S(SR, SA, SB); 146 goto pack_s; 147 148 case FOP_FNC_DIVx: 149 FP_DIV_S(SR, SA, SB); 150 goto pack_s; 151 152 case FOP_FNC_SQRTx: 153 FP_SQRT_S(SR, SB); 154 goto pack_s; 155 } 156 goto bad_insn; 157 158 case FOP_SRC_T: 159 va = alpha_read_fp_reg(fa); 160 vb = alpha_read_fp_reg(fb); 161 162 if ((func & ~3) == FOP_FNC_CMPxUN) { 163 FP_UNPACK_RAW_DP(DA, &va); 164 FP_UNPACK_RAW_DP(DB, &vb); 165 if (!DA_e && !_FP_FRAC_ZEROP_1(DA)) { 166 FP_SET_EXCEPTION(FP_EX_DENORM); 167 if (FP_DENORM_ZERO) 168 _FP_FRAC_SET_1(DA, _FP_ZEROFRAC_1); 169 } 170 if (!DB_e && !_FP_FRAC_ZEROP_1(DB)) { 171 FP_SET_EXCEPTION(FP_EX_DENORM); 172 if (FP_DENORM_ZERO) 173 _FP_FRAC_SET_1(DB, _FP_ZEROFRAC_1); 174 } 175 FP_CMP_D(res, DA, DB, 3); 176 vc = 0x4000000000000000UL; 177 /* CMPTEQ, CMPTUN don't trap on QNaN, 178 while CMPTLT and CMPTLE do */ 179 if (res == 3 180 && ((func & 3) >= 2 181 || FP_ISSIGNAN_D(DA) 182 || FP_ISSIGNAN_D(DB))) { 183 FP_SET_EXCEPTION(FP_EX_INVALID); 184 } 185 switch (func) { 186 case FOP_FNC_CMPxUN: if (res != 3) vc = 0; break; 187 case FOP_FNC_CMPxEQ: if (res) vc = 0; break; 188 case FOP_FNC_CMPxLT: if (res != -1) vc = 0; break; 189 case FOP_FNC_CMPxLE: if ((long)res > 0) vc = 0; break; 190 } 191 goto done_d; 192 } 193 194 FP_UNPACK_DP(DA, &va); 195 FP_UNPACK_DP(DB, &vb); 196 197 switch (func) { 198 case FOP_FNC_SUBx: 199 FP_SUB_D(DR, DA, DB); 200 goto pack_d; 201 202 case FOP_FNC_ADDx: 203 FP_ADD_D(DR, DA, DB); 204 goto pack_d; 205 206 case FOP_FNC_MULx: 207 FP_MUL_D(DR, DA, DB); 208 goto pack_d; 209 210 case FOP_FNC_DIVx: 211 FP_DIV_D(DR, DA, DB); 212 goto pack_d; 213 214 case FOP_FNC_SQRTx: 215 FP_SQRT_D(DR, DB); 216 goto pack_d; 217 218 case FOP_FNC_CVTxS: 219 /* It is irritating that DEC encoded CVTST with 220 SRC == T_floating. It is also interesting that 221 the bit used to tell the two apart is /U... */ 222 if (insn & 0x2000) { 223 FP_CONV(S,D,1,1,SR,DB); 224 goto pack_s; 225 } else { 226 vb = alpha_read_fp_reg_s(fb); 227 FP_UNPACK_SP(SB, &vb); 228 DR_c = DB_c; 229 DR_s = DB_s; 230 DR_e = DB_e + (1024 - 128); 231 DR_f = SB_f << (52 - 23); 232 goto pack_d; 233 } 234 235 case FOP_FNC_CVTxQ: 236 if (DB_c == FP_CLS_NAN 237 && (_FP_FRAC_HIGH_RAW_D(DB) & _FP_QNANBIT_D)) { 238 /* AAHB Table B-2 says QNaN should not trigger INV */ 239 vc = 0; 240 } else 241 FP_TO_INT_ROUND_D(vc, DB, 64, 2); 242 goto done_d; 243 } 244 goto bad_insn; 245 246 case FOP_SRC_Q: 247 vb = alpha_read_fp_reg(fb); 248 249 switch (func) { 250 case FOP_FNC_CVTQL: 251 /* Notice: We can get here only due to an integer 252 overflow. Such overflows are reported as invalid 253 ops. We return the result the hw would have 254 computed. */ 255 vc = ((vb & 0xc0000000) << 32 | /* sign and msb */ 256 (vb & 0x3fffffff) << 29); /* rest of the int */ 257 FP_SET_EXCEPTION (FP_EX_INVALID); 258 goto done_d; 259 260 case FOP_FNC_CVTxS: 261 FP_FROM_INT_S(SR, ((long)vb), 64, long); 262 goto pack_s; 263 264 case FOP_FNC_CVTxT: 265 FP_FROM_INT_D(DR, ((long)vb), 64, long); 266 goto pack_d; 267 } 268 goto bad_insn; 269 } 270 goto bad_insn; 271 272 pack_s: 273 FP_PACK_SP(&vc, SR); 274 if ((_fex & FP_EX_UNDERFLOW) && (swcr & IEEE_MAP_UMZ)) 275 vc = 0; 276 alpha_write_fp_reg_s(fc, vc); 277 goto done; 278 279 pack_d: 280 FP_PACK_DP(&vc, DR); 281 if ((_fex & FP_EX_UNDERFLOW) && (swcr & IEEE_MAP_UMZ)) 282 vc = 0; 283 done_d: 284 alpha_write_fp_reg(fc, vc); 285 goto done; 286 287 /* 288 * Take the appropriate action for each possible 289 * floating-point result: 290 * 291 * - Set the appropriate bits in the FPCR 292 * - If the specified exception is enabled in the FPCR, 293 * return. The caller (entArith) will dispatch 294 * the appropriate signal to the translated program. 295 * 296 * In addition, properly track the exception state in software 297 * as described in the Alpha Architecture Handbook section 4.7.7.3. 298 */ 299 done: 300 if (_fex) { 301 /* Record exceptions in software control word. */ 302 swcr |= (_fex << IEEE_STATUS_TO_EXCSUM_SHIFT); 303 current_thread_info()->ieee_state 304 |= (_fex << IEEE_STATUS_TO_EXCSUM_SHIFT); 305 306 /* Update hardware control register. */ 307 fpcr &= (~FPCR_MASK | FPCR_DYN_MASK); 308 fpcr |= ieee_swcr_to_fpcr(swcr); 309 wrfpcr(fpcr); 310 311 /* Do we generate a signal? */ 312 _fex = _fex & swcr & IEEE_TRAP_ENABLE_MASK; 313 si_code = 0; 314 if (_fex) { 315 if (_fex & IEEE_TRAP_ENABLE_DNO) si_code = FPE_FLTUND; 316 if (_fex & IEEE_TRAP_ENABLE_INE) si_code = FPE_FLTRES; 317 if (_fex & IEEE_TRAP_ENABLE_UNF) si_code = FPE_FLTUND; 318 if (_fex & IEEE_TRAP_ENABLE_OVF) si_code = FPE_FLTOVF; 319 if (_fex & IEEE_TRAP_ENABLE_DZE) si_code = FPE_FLTDIV; 320 if (_fex & IEEE_TRAP_ENABLE_INV) si_code = FPE_FLTINV; 321 } 322 323 return si_code; 324 } 325 326 /* We used to write the destination register here, but DEC FORTRAN 327 requires that the result *always* be written... so we do the write 328 immediately after the operations above. */ 329 330 return 0; 331 332 bad_insn: 333 printk(KERN_ERR "alpha_fp_emul: Invalid FP insn %#x at %#lx\n", 334 insn, pc); 335 return -1; 336 } 337 338 long 339 alpha_fp_emul_imprecise (struct pt_regs *regs, unsigned long write_mask) 340 { 341 unsigned long trigger_pc = regs->pc - 4; 342 unsigned long insn, opcode, rc, si_code = 0; 343 344 /* 345 * Turn off the bits corresponding to registers that are the 346 * target of instructions that set bits in the exception 347 * summary register. We have some slack doing this because a 348 * register that is the target of a trapping instruction can 349 * be written at most once in the trap shadow. 350 * 351 * Branches, jumps, TRAPBs, EXCBs and calls to PALcode all 352 * bound the trap shadow, so we need not look any further than 353 * up to the first occurrence of such an instruction. 354 */ 355 while (write_mask) { 356 get_user(insn, (__u32 __user *)(trigger_pc)); 357 opcode = insn >> 26; 358 rc = insn & 0x1f; 359 360 switch (opcode) { 361 case OPC_PAL: 362 case OPC_JSR: 363 case 0x30 ... 0x3f: /* branches */ 364 goto egress; 365 366 case OPC_MISC: 367 switch (insn & 0xffff) { 368 case MISC_TRAPB: 369 case MISC_EXCB: 370 goto egress; 371 372 default: 373 break; 374 } 375 break; 376 377 case OPC_INTA: 378 case OPC_INTL: 379 case OPC_INTS: 380 case OPC_INTM: 381 write_mask &= ~(1UL << rc); 382 break; 383 384 case OPC_FLTC: 385 case OPC_FLTV: 386 case OPC_FLTI: 387 case OPC_FLTL: 388 write_mask &= ~(1UL << (rc + 32)); 389 break; 390 } 391 if (!write_mask) { 392 /* Re-execute insns in the trap-shadow. */ 393 regs->pc = trigger_pc + 4; 394 si_code = alpha_fp_emul(trigger_pc); 395 goto egress; 396 } 397 trigger_pc -= 4; 398 } 399 400 egress: 401 return si_code; 402 } 403