1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * arch/alpha/kernel/traps.c 4 * 5 * (C) Copyright 1994 Linus Torvalds 6 */ 7 8 /* 9 * This file initializes the trap entry points 10 */ 11 12 #include <linux/jiffies.h> 13 #include <linux/mm.h> 14 #include <linux/sched/signal.h> 15 #include <linux/sched/debug.h> 16 #include <linux/tty.h> 17 #include <linux/delay.h> 18 #include <linux/extable.h> 19 #include <linux/kallsyms.h> 20 #include <linux/ratelimit.h> 21 22 #include <asm/gentrap.h> 23 #include <linux/uaccess.h> 24 #include <asm/unaligned.h> 25 #include <asm/sysinfo.h> 26 #include <asm/hwrpb.h> 27 #include <asm/mmu_context.h> 28 #include <asm/special_insns.h> 29 30 #include "proto.h" 31 32 /* Work-around for some SRMs which mishandle opDEC faults. */ 33 34 static int opDEC_fix; 35 36 static void 37 opDEC_check(void) 38 { 39 __asm__ __volatile__ ( 40 /* Load the address of... */ 41 " br $16, 1f\n" 42 /* A stub instruction fault handler. Just add 4 to the 43 pc and continue. */ 44 " ldq $16, 8($sp)\n" 45 " addq $16, 4, $16\n" 46 " stq $16, 8($sp)\n" 47 " call_pal %[rti]\n" 48 /* Install the instruction fault handler. */ 49 "1: lda $17, 3\n" 50 " call_pal %[wrent]\n" 51 /* With that in place, the fault from the round-to-minf fp 52 insn will arrive either at the "lda 4" insn (bad) or one 53 past that (good). This places the correct fixup in %0. */ 54 " lda %[fix], 0\n" 55 " cvttq/svm $f31,$f31\n" 56 " lda %[fix], 4" 57 : [fix] "=r" (opDEC_fix) 58 : [rti] "n" (PAL_rti), [wrent] "n" (PAL_wrent) 59 : "$0", "$1", "$16", "$17", "$22", "$23", "$24", "$25"); 60 61 if (opDEC_fix) 62 printk("opDEC fixup enabled.\n"); 63 } 64 65 void 66 dik_show_regs(struct pt_regs *regs, unsigned long *r9_15) 67 { 68 printk("pc = [<%016lx>] ra = [<%016lx>] ps = %04lx %s\n", 69 regs->pc, regs->r26, regs->ps, print_tainted()); 70 printk("pc is at %pSR\n", (void *)regs->pc); 71 printk("ra is at %pSR\n", (void *)regs->r26); 72 printk("v0 = %016lx t0 = %016lx t1 = %016lx\n", 73 regs->r0, regs->r1, regs->r2); 74 printk("t2 = %016lx t3 = %016lx t4 = %016lx\n", 75 regs->r3, regs->r4, regs->r5); 76 printk("t5 = %016lx t6 = %016lx t7 = %016lx\n", 77 regs->r6, regs->r7, regs->r8); 78 79 if (r9_15) { 80 printk("s0 = %016lx s1 = %016lx s2 = %016lx\n", 81 r9_15[9], r9_15[10], r9_15[11]); 82 printk("s3 = %016lx s4 = %016lx s5 = %016lx\n", 83 r9_15[12], r9_15[13], r9_15[14]); 84 printk("s6 = %016lx\n", r9_15[15]); 85 } 86 87 printk("a0 = %016lx a1 = %016lx a2 = %016lx\n", 88 regs->r16, regs->r17, regs->r18); 89 printk("a3 = %016lx a4 = %016lx a5 = %016lx\n", 90 regs->r19, regs->r20, regs->r21); 91 printk("t8 = %016lx t9 = %016lx t10= %016lx\n", 92 regs->r22, regs->r23, regs->r24); 93 printk("t11= %016lx pv = %016lx at = %016lx\n", 94 regs->r25, regs->r27, regs->r28); 95 printk("gp = %016lx sp = %p\n", regs->gp, regs+1); 96 #if 0 97 __halt(); 98 #endif 99 } 100 101 #if 0 102 static char * ireg_name[] = {"v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", 103 "t7", "s0", "s1", "s2", "s3", "s4", "s5", "s6", 104 "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", 105 "t10", "t11", "ra", "pv", "at", "gp", "sp", "zero"}; 106 #endif 107 108 static void 109 dik_show_code(unsigned int *pc) 110 { 111 long i; 112 113 printk("Code:"); 114 for (i = -6; i < 2; i++) { 115 unsigned int insn; 116 if (__get_user(insn, (unsigned int __user *)pc + i)) 117 break; 118 printk("%c%08x%c", i ? ' ' : '<', insn, i ? ' ' : '>'); 119 } 120 printk("\n"); 121 } 122 123 static void 124 dik_show_trace(unsigned long *sp) 125 { 126 long i = 0; 127 printk("Trace:\n"); 128 while (0x1ff8 & (unsigned long) sp) { 129 extern char _stext[], _etext[]; 130 unsigned long tmp = *sp; 131 sp++; 132 if (tmp < (unsigned long) &_stext) 133 continue; 134 if (tmp >= (unsigned long) &_etext) 135 continue; 136 printk("[<%lx>] %pSR\n", tmp, (void *)tmp); 137 if (i > 40) { 138 printk(" ..."); 139 break; 140 } 141 } 142 printk("\n"); 143 } 144 145 static int kstack_depth_to_print = 24; 146 147 void show_stack(struct task_struct *task, unsigned long *sp) 148 { 149 unsigned long *stack; 150 int i; 151 152 /* 153 * debugging aid: "show_stack(NULL);" prints the 154 * back trace for this cpu. 155 */ 156 if(sp==NULL) 157 sp=(unsigned long*)&sp; 158 159 stack = sp; 160 for(i=0; i < kstack_depth_to_print; i++) { 161 if (((long) stack & (THREAD_SIZE-1)) == 0) 162 break; 163 if ((i % 4) == 0) { 164 if (i) 165 pr_cont("\n"); 166 printk(" "); 167 } else { 168 pr_cont(" "); 169 } 170 pr_cont("%016lx", *stack++); 171 } 172 pr_cont("\n"); 173 dik_show_trace(sp); 174 } 175 176 void 177 die_if_kernel(char * str, struct pt_regs *regs, long err, unsigned long *r9_15) 178 { 179 if (regs->ps & 8) 180 return; 181 #ifdef CONFIG_SMP 182 printk("CPU %d ", hard_smp_processor_id()); 183 #endif 184 printk("%s(%d): %s %ld\n", current->comm, task_pid_nr(current), str, err); 185 dik_show_regs(regs, r9_15); 186 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 187 dik_show_trace((unsigned long *)(regs+1)); 188 dik_show_code((unsigned int *)regs->pc); 189 190 if (test_and_set_thread_flag (TIF_DIE_IF_KERNEL)) { 191 printk("die_if_kernel recursion detected.\n"); 192 local_irq_enable(); 193 while (1); 194 } 195 do_exit(SIGSEGV); 196 } 197 198 #ifndef CONFIG_MATHEMU 199 static long dummy_emul(void) { return 0; } 200 long (*alpha_fp_emul_imprecise)(struct pt_regs *regs, unsigned long writemask) 201 = (void *)dummy_emul; 202 EXPORT_SYMBOL_GPL(alpha_fp_emul_imprecise); 203 long (*alpha_fp_emul) (unsigned long pc) 204 = (void *)dummy_emul; 205 EXPORT_SYMBOL_GPL(alpha_fp_emul); 206 #else 207 long alpha_fp_emul_imprecise(struct pt_regs *regs, unsigned long writemask); 208 long alpha_fp_emul (unsigned long pc); 209 #endif 210 211 asmlinkage void 212 do_entArith(unsigned long summary, unsigned long write_mask, 213 struct pt_regs *regs) 214 { 215 long si_code = FPE_FLTINV; 216 siginfo_t info; 217 218 if (summary & 1) { 219 /* Software-completion summary bit is set, so try to 220 emulate the instruction. If the processor supports 221 precise exceptions, we don't have to search. */ 222 if (!amask(AMASK_PRECISE_TRAP)) 223 si_code = alpha_fp_emul(regs->pc - 4); 224 else 225 si_code = alpha_fp_emul_imprecise(regs, write_mask); 226 if (si_code == 0) 227 return; 228 } 229 die_if_kernel("Arithmetic fault", regs, 0, NULL); 230 231 info.si_signo = SIGFPE; 232 info.si_errno = 0; 233 info.si_code = si_code; 234 info.si_addr = (void __user *) regs->pc; 235 send_sig_info(SIGFPE, &info, current); 236 } 237 238 asmlinkage void 239 do_entIF(unsigned long type, struct pt_regs *regs) 240 { 241 siginfo_t info; 242 int signo, code; 243 244 if ((regs->ps & ~IPL_MAX) == 0) { 245 if (type == 1) { 246 const unsigned int *data 247 = (const unsigned int *) regs->pc; 248 printk("Kernel bug at %s:%d\n", 249 (const char *)(data[1] | (long)data[2] << 32), 250 data[0]); 251 } 252 #ifdef CONFIG_ALPHA_WTINT 253 if (type == 4) { 254 /* If CALL_PAL WTINT is totally unsupported by the 255 PALcode, e.g. MILO, "emulate" it by overwriting 256 the insn. */ 257 unsigned int *pinsn 258 = (unsigned int *) regs->pc - 1; 259 if (*pinsn == PAL_wtint) { 260 *pinsn = 0x47e01400; /* mov 0,$0 */ 261 imb(); 262 regs->r0 = 0; 263 return; 264 } 265 } 266 #endif /* ALPHA_WTINT */ 267 die_if_kernel((type == 1 ? "Kernel Bug" : "Instruction fault"), 268 regs, type, NULL); 269 } 270 271 switch (type) { 272 case 0: /* breakpoint */ 273 info.si_signo = SIGTRAP; 274 info.si_errno = 0; 275 info.si_code = TRAP_BRKPT; 276 info.si_trapno = 0; 277 info.si_addr = (void __user *) regs->pc; 278 279 if (ptrace_cancel_bpt(current)) { 280 regs->pc -= 4; /* make pc point to former bpt */ 281 } 282 283 send_sig_info(SIGTRAP, &info, current); 284 return; 285 286 case 1: /* bugcheck */ 287 info.si_signo = SIGTRAP; 288 info.si_errno = 0; 289 info.si_code = TRAP_FIXME; 290 info.si_addr = (void __user *) regs->pc; 291 info.si_trapno = 0; 292 send_sig_info(SIGTRAP, &info, current); 293 return; 294 295 case 2: /* gentrap */ 296 info.si_addr = (void __user *) regs->pc; 297 info.si_trapno = regs->r16; 298 switch ((long) regs->r16) { 299 case GEN_INTOVF: 300 signo = SIGFPE; 301 code = FPE_INTOVF; 302 break; 303 case GEN_INTDIV: 304 signo = SIGFPE; 305 code = FPE_INTDIV; 306 break; 307 case GEN_FLTOVF: 308 signo = SIGFPE; 309 code = FPE_FLTOVF; 310 break; 311 case GEN_FLTDIV: 312 signo = SIGFPE; 313 code = FPE_FLTDIV; 314 break; 315 case GEN_FLTUND: 316 signo = SIGFPE; 317 code = FPE_FLTUND; 318 break; 319 case GEN_FLTINV: 320 signo = SIGFPE; 321 code = FPE_FLTINV; 322 break; 323 case GEN_FLTINE: 324 signo = SIGFPE; 325 code = FPE_FLTRES; 326 break; 327 case GEN_ROPRAND: 328 signo = SIGFPE; 329 code = FPE_FIXME; 330 break; 331 332 case GEN_DECOVF: 333 case GEN_DECDIV: 334 case GEN_DECINV: 335 case GEN_ASSERTERR: 336 case GEN_NULPTRERR: 337 case GEN_STKOVF: 338 case GEN_STRLENERR: 339 case GEN_SUBSTRERR: 340 case GEN_RANGERR: 341 case GEN_SUBRNG: 342 case GEN_SUBRNG1: 343 case GEN_SUBRNG2: 344 case GEN_SUBRNG3: 345 case GEN_SUBRNG4: 346 case GEN_SUBRNG5: 347 case GEN_SUBRNG6: 348 case GEN_SUBRNG7: 349 default: 350 signo = SIGTRAP; 351 code = TRAP_FIXME; 352 break; 353 } 354 355 info.si_signo = signo; 356 info.si_errno = 0; 357 info.si_code = code; 358 info.si_addr = (void __user *) regs->pc; 359 send_sig_info(signo, &info, current); 360 return; 361 362 case 4: /* opDEC */ 363 if (implver() == IMPLVER_EV4) { 364 long si_code; 365 366 /* The some versions of SRM do not handle 367 the opDEC properly - they return the PC of the 368 opDEC fault, not the instruction after as the 369 Alpha architecture requires. Here we fix it up. 370 We do this by intentionally causing an opDEC 371 fault during the boot sequence and testing if 372 we get the correct PC. If not, we set a flag 373 to correct it every time through. */ 374 regs->pc += opDEC_fix; 375 376 /* EV4 does not implement anything except normal 377 rounding. Everything else will come here as 378 an illegal instruction. Emulate them. */ 379 si_code = alpha_fp_emul(regs->pc - 4); 380 if (si_code == 0) 381 return; 382 if (si_code > 0) { 383 info.si_signo = SIGFPE; 384 info.si_errno = 0; 385 info.si_code = si_code; 386 info.si_addr = (void __user *) regs->pc; 387 send_sig_info(SIGFPE, &info, current); 388 return; 389 } 390 } 391 break; 392 393 case 3: /* FEN fault */ 394 /* Irritating users can call PAL_clrfen to disable the 395 FPU for the process. The kernel will then trap in 396 do_switch_stack and undo_switch_stack when we try 397 to save and restore the FP registers. 398 399 Given that GCC by default generates code that uses the 400 FP registers, PAL_clrfen is not useful except for DoS 401 attacks. So turn the bleeding FPU back on and be done 402 with it. */ 403 current_thread_info()->pcb.flags |= 1; 404 __reload_thread(¤t_thread_info()->pcb); 405 return; 406 407 case 5: /* illoc */ 408 default: /* unexpected instruction-fault type */ 409 ; 410 } 411 412 info.si_signo = SIGILL; 413 info.si_errno = 0; 414 info.si_code = ILL_ILLOPC; 415 info.si_addr = (void __user *) regs->pc; 416 send_sig_info(SIGILL, &info, current); 417 } 418 419 /* There is an ifdef in the PALcode in MILO that enables a 420 "kernel debugging entry point" as an unprivileged call_pal. 421 422 We don't want to have anything to do with it, but unfortunately 423 several versions of MILO included in distributions have it enabled, 424 and if we don't put something on the entry point we'll oops. */ 425 426 asmlinkage void 427 do_entDbg(struct pt_regs *regs) 428 { 429 siginfo_t info; 430 431 die_if_kernel("Instruction fault", regs, 0, NULL); 432 433 info.si_signo = SIGILL; 434 info.si_errno = 0; 435 info.si_code = ILL_ILLOPC; 436 info.si_addr = (void __user *) regs->pc; 437 force_sig_info(SIGILL, &info, current); 438 } 439 440 441 /* 442 * entUna has a different register layout to be reasonably simple. It 443 * needs access to all the integer registers (the kernel doesn't use 444 * fp-regs), and it needs to have them in order for simpler access. 445 * 446 * Due to the non-standard register layout (and because we don't want 447 * to handle floating-point regs), user-mode unaligned accesses are 448 * handled separately by do_entUnaUser below. 449 * 450 * Oh, btw, we don't handle the "gp" register correctly, but if we fault 451 * on a gp-register unaligned load/store, something is _very_ wrong 452 * in the kernel anyway.. 453 */ 454 struct allregs { 455 unsigned long regs[32]; 456 unsigned long ps, pc, gp, a0, a1, a2; 457 }; 458 459 struct unaligned_stat { 460 unsigned long count, va, pc; 461 } unaligned[2]; 462 463 464 /* Macro for exception fixup code to access integer registers. */ 465 #define una_reg(r) (_regs[(r) >= 16 && (r) <= 18 ? (r)+19 : (r)]) 466 467 468 asmlinkage void 469 do_entUna(void * va, unsigned long opcode, unsigned long reg, 470 struct allregs *regs) 471 { 472 long error, tmp1, tmp2, tmp3, tmp4; 473 unsigned long pc = regs->pc - 4; 474 unsigned long *_regs = regs->regs; 475 const struct exception_table_entry *fixup; 476 477 unaligned[0].count++; 478 unaligned[0].va = (unsigned long) va; 479 unaligned[0].pc = pc; 480 481 /* We don't want to use the generic get/put unaligned macros as 482 we want to trap exceptions. Only if we actually get an 483 exception will we decide whether we should have caught it. */ 484 485 switch (opcode) { 486 case 0x0c: /* ldwu */ 487 __asm__ __volatile__( 488 "1: ldq_u %1,0(%3)\n" 489 "2: ldq_u %2,1(%3)\n" 490 " extwl %1,%3,%1\n" 491 " extwh %2,%3,%2\n" 492 "3:\n" 493 EXC(1b,3b,%1,%0) 494 EXC(2b,3b,%2,%0) 495 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2) 496 : "r"(va), "0"(0)); 497 if (error) 498 goto got_exception; 499 una_reg(reg) = tmp1|tmp2; 500 return; 501 502 case 0x28: /* ldl */ 503 __asm__ __volatile__( 504 "1: ldq_u %1,0(%3)\n" 505 "2: ldq_u %2,3(%3)\n" 506 " extll %1,%3,%1\n" 507 " extlh %2,%3,%2\n" 508 "3:\n" 509 EXC(1b,3b,%1,%0) 510 EXC(2b,3b,%2,%0) 511 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2) 512 : "r"(va), "0"(0)); 513 if (error) 514 goto got_exception; 515 una_reg(reg) = (int)(tmp1|tmp2); 516 return; 517 518 case 0x29: /* ldq */ 519 __asm__ __volatile__( 520 "1: ldq_u %1,0(%3)\n" 521 "2: ldq_u %2,7(%3)\n" 522 " extql %1,%3,%1\n" 523 " extqh %2,%3,%2\n" 524 "3:\n" 525 EXC(1b,3b,%1,%0) 526 EXC(2b,3b,%2,%0) 527 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2) 528 : "r"(va), "0"(0)); 529 if (error) 530 goto got_exception; 531 una_reg(reg) = tmp1|tmp2; 532 return; 533 534 /* Note that the store sequences do not indicate that they change 535 memory because it _should_ be affecting nothing in this context. 536 (Otherwise we have other, much larger, problems.) */ 537 case 0x0d: /* stw */ 538 __asm__ __volatile__( 539 "1: ldq_u %2,1(%5)\n" 540 "2: ldq_u %1,0(%5)\n" 541 " inswh %6,%5,%4\n" 542 " inswl %6,%5,%3\n" 543 " mskwh %2,%5,%2\n" 544 " mskwl %1,%5,%1\n" 545 " or %2,%4,%2\n" 546 " or %1,%3,%1\n" 547 "3: stq_u %2,1(%5)\n" 548 "4: stq_u %1,0(%5)\n" 549 "5:\n" 550 EXC(1b,5b,%2,%0) 551 EXC(2b,5b,%1,%0) 552 EXC(3b,5b,$31,%0) 553 EXC(4b,5b,$31,%0) 554 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2), 555 "=&r"(tmp3), "=&r"(tmp4) 556 : "r"(va), "r"(una_reg(reg)), "0"(0)); 557 if (error) 558 goto got_exception; 559 return; 560 561 case 0x2c: /* stl */ 562 __asm__ __volatile__( 563 "1: ldq_u %2,3(%5)\n" 564 "2: ldq_u %1,0(%5)\n" 565 " inslh %6,%5,%4\n" 566 " insll %6,%5,%3\n" 567 " msklh %2,%5,%2\n" 568 " mskll %1,%5,%1\n" 569 " or %2,%4,%2\n" 570 " or %1,%3,%1\n" 571 "3: stq_u %2,3(%5)\n" 572 "4: stq_u %1,0(%5)\n" 573 "5:\n" 574 EXC(1b,5b,%2,%0) 575 EXC(2b,5b,%1,%0) 576 EXC(3b,5b,$31,%0) 577 EXC(4b,5b,$31,%0) 578 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2), 579 "=&r"(tmp3), "=&r"(tmp4) 580 : "r"(va), "r"(una_reg(reg)), "0"(0)); 581 if (error) 582 goto got_exception; 583 return; 584 585 case 0x2d: /* stq */ 586 __asm__ __volatile__( 587 "1: ldq_u %2,7(%5)\n" 588 "2: ldq_u %1,0(%5)\n" 589 " insqh %6,%5,%4\n" 590 " insql %6,%5,%3\n" 591 " mskqh %2,%5,%2\n" 592 " mskql %1,%5,%1\n" 593 " or %2,%4,%2\n" 594 " or %1,%3,%1\n" 595 "3: stq_u %2,7(%5)\n" 596 "4: stq_u %1,0(%5)\n" 597 "5:\n" 598 EXC(1b,5b,%2,%0) 599 EXC(2b,5b,%1,%0) 600 EXC(3b,5b,$31,%0) 601 EXC(4b,5b,$31,%0) 602 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2), 603 "=&r"(tmp3), "=&r"(tmp4) 604 : "r"(va), "r"(una_reg(reg)), "0"(0)); 605 if (error) 606 goto got_exception; 607 return; 608 } 609 610 printk("Bad unaligned kernel access at %016lx: %p %lx %lu\n", 611 pc, va, opcode, reg); 612 do_exit(SIGSEGV); 613 614 got_exception: 615 /* Ok, we caught the exception, but we don't want it. Is there 616 someone to pass it along to? */ 617 if ((fixup = search_exception_tables(pc)) != 0) { 618 unsigned long newpc; 619 newpc = fixup_exception(una_reg, fixup, pc); 620 621 printk("Forwarding unaligned exception at %lx (%lx)\n", 622 pc, newpc); 623 624 regs->pc = newpc; 625 return; 626 } 627 628 /* 629 * Yikes! No one to forward the exception to. 630 * Since the registers are in a weird format, dump them ourselves. 631 */ 632 633 printk("%s(%d): unhandled unaligned exception\n", 634 current->comm, task_pid_nr(current)); 635 636 printk("pc = [<%016lx>] ra = [<%016lx>] ps = %04lx\n", 637 pc, una_reg(26), regs->ps); 638 printk("r0 = %016lx r1 = %016lx r2 = %016lx\n", 639 una_reg(0), una_reg(1), una_reg(2)); 640 printk("r3 = %016lx r4 = %016lx r5 = %016lx\n", 641 una_reg(3), una_reg(4), una_reg(5)); 642 printk("r6 = %016lx r7 = %016lx r8 = %016lx\n", 643 una_reg(6), una_reg(7), una_reg(8)); 644 printk("r9 = %016lx r10= %016lx r11= %016lx\n", 645 una_reg(9), una_reg(10), una_reg(11)); 646 printk("r12= %016lx r13= %016lx r14= %016lx\n", 647 una_reg(12), una_reg(13), una_reg(14)); 648 printk("r15= %016lx\n", una_reg(15)); 649 printk("r16= %016lx r17= %016lx r18= %016lx\n", 650 una_reg(16), una_reg(17), una_reg(18)); 651 printk("r19= %016lx r20= %016lx r21= %016lx\n", 652 una_reg(19), una_reg(20), una_reg(21)); 653 printk("r22= %016lx r23= %016lx r24= %016lx\n", 654 una_reg(22), una_reg(23), una_reg(24)); 655 printk("r25= %016lx r27= %016lx r28= %016lx\n", 656 una_reg(25), una_reg(27), una_reg(28)); 657 printk("gp = %016lx sp = %p\n", regs->gp, regs+1); 658 659 dik_show_code((unsigned int *)pc); 660 dik_show_trace((unsigned long *)(regs+1)); 661 662 if (test_and_set_thread_flag (TIF_DIE_IF_KERNEL)) { 663 printk("die_if_kernel recursion detected.\n"); 664 local_irq_enable(); 665 while (1); 666 } 667 do_exit(SIGSEGV); 668 } 669 670 /* 671 * Convert an s-floating point value in memory format to the 672 * corresponding value in register format. The exponent 673 * needs to be remapped to preserve non-finite values 674 * (infinities, not-a-numbers, denormals). 675 */ 676 static inline unsigned long 677 s_mem_to_reg (unsigned long s_mem) 678 { 679 unsigned long frac = (s_mem >> 0) & 0x7fffff; 680 unsigned long sign = (s_mem >> 31) & 0x1; 681 unsigned long exp_msb = (s_mem >> 30) & 0x1; 682 unsigned long exp_low = (s_mem >> 23) & 0x7f; 683 unsigned long exp; 684 685 exp = (exp_msb << 10) | exp_low; /* common case */ 686 if (exp_msb) { 687 if (exp_low == 0x7f) { 688 exp = 0x7ff; 689 } 690 } else { 691 if (exp_low == 0x00) { 692 exp = 0x000; 693 } else { 694 exp |= (0x7 << 7); 695 } 696 } 697 return (sign << 63) | (exp << 52) | (frac << 29); 698 } 699 700 /* 701 * Convert an s-floating point value in register format to the 702 * corresponding value in memory format. 703 */ 704 static inline unsigned long 705 s_reg_to_mem (unsigned long s_reg) 706 { 707 return ((s_reg >> 62) << 30) | ((s_reg << 5) >> 34); 708 } 709 710 /* 711 * Handle user-level unaligned fault. Handling user-level unaligned 712 * faults is *extremely* slow and produces nasty messages. A user 713 * program *should* fix unaligned faults ASAP. 714 * 715 * Notice that we have (almost) the regular kernel stack layout here, 716 * so finding the appropriate registers is a little more difficult 717 * than in the kernel case. 718 * 719 * Finally, we handle regular integer load/stores only. In 720 * particular, load-linked/store-conditionally and floating point 721 * load/stores are not supported. The former make no sense with 722 * unaligned faults (they are guaranteed to fail) and I don't think 723 * the latter will occur in any decent program. 724 * 725 * Sigh. We *do* have to handle some FP operations, because GCC will 726 * uses them as temporary storage for integer memory to memory copies. 727 * However, we need to deal with stt/ldt and sts/lds only. 728 */ 729 730 #define OP_INT_MASK ( 1L << 0x28 | 1L << 0x2c /* ldl stl */ \ 731 | 1L << 0x29 | 1L << 0x2d /* ldq stq */ \ 732 | 1L << 0x0c | 1L << 0x0d /* ldwu stw */ \ 733 | 1L << 0x0a | 1L << 0x0e ) /* ldbu stb */ 734 735 #define OP_WRITE_MASK ( 1L << 0x26 | 1L << 0x27 /* sts stt */ \ 736 | 1L << 0x2c | 1L << 0x2d /* stl stq */ \ 737 | 1L << 0x0d | 1L << 0x0e ) /* stw stb */ 738 739 #define R(x) ((size_t) &((struct pt_regs *)0)->x) 740 741 static int unauser_reg_offsets[32] = { 742 R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), R(r8), 743 /* r9 ... r15 are stored in front of regs. */ 744 -56, -48, -40, -32, -24, -16, -8, 745 R(r16), R(r17), R(r18), 746 R(r19), R(r20), R(r21), R(r22), R(r23), R(r24), R(r25), R(r26), 747 R(r27), R(r28), R(gp), 748 0, 0 749 }; 750 751 #undef R 752 753 asmlinkage void 754 do_entUnaUser(void __user * va, unsigned long opcode, 755 unsigned long reg, struct pt_regs *regs) 756 { 757 static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5); 758 759 unsigned long tmp1, tmp2, tmp3, tmp4; 760 unsigned long fake_reg, *reg_addr = &fake_reg; 761 siginfo_t info; 762 long error; 763 764 /* Check the UAC bits to decide what the user wants us to do 765 with the unaliged access. */ 766 767 if (!(current_thread_info()->status & TS_UAC_NOPRINT)) { 768 if (__ratelimit(&ratelimit)) { 769 printk("%s(%d): unaligned trap at %016lx: %p %lx %ld\n", 770 current->comm, task_pid_nr(current), 771 regs->pc - 4, va, opcode, reg); 772 } 773 } 774 if ((current_thread_info()->status & TS_UAC_SIGBUS)) 775 goto give_sigbus; 776 /* Not sure why you'd want to use this, but... */ 777 if ((current_thread_info()->status & TS_UAC_NOFIX)) 778 return; 779 780 /* Don't bother reading ds in the access check since we already 781 know that this came from the user. Also rely on the fact that 782 the page at TASK_SIZE is unmapped and so can't be touched anyway. */ 783 if ((unsigned long)va >= TASK_SIZE) 784 goto give_sigsegv; 785 786 ++unaligned[1].count; 787 unaligned[1].va = (unsigned long)va; 788 unaligned[1].pc = regs->pc - 4; 789 790 if ((1L << opcode) & OP_INT_MASK) { 791 /* it's an integer load/store */ 792 if (reg < 30) { 793 reg_addr = (unsigned long *) 794 ((char *)regs + unauser_reg_offsets[reg]); 795 } else if (reg == 30) { 796 /* usp in PAL regs */ 797 fake_reg = rdusp(); 798 } else { 799 /* zero "register" */ 800 fake_reg = 0; 801 } 802 } 803 804 /* We don't want to use the generic get/put unaligned macros as 805 we want to trap exceptions. Only if we actually get an 806 exception will we decide whether we should have caught it. */ 807 808 switch (opcode) { 809 case 0x0c: /* ldwu */ 810 __asm__ __volatile__( 811 "1: ldq_u %1,0(%3)\n" 812 "2: ldq_u %2,1(%3)\n" 813 " extwl %1,%3,%1\n" 814 " extwh %2,%3,%2\n" 815 "3:\n" 816 EXC(1b,3b,%1,%0) 817 EXC(2b,3b,%2,%0) 818 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2) 819 : "r"(va), "0"(0)); 820 if (error) 821 goto give_sigsegv; 822 *reg_addr = tmp1|tmp2; 823 break; 824 825 case 0x22: /* lds */ 826 __asm__ __volatile__( 827 "1: ldq_u %1,0(%3)\n" 828 "2: ldq_u %2,3(%3)\n" 829 " extll %1,%3,%1\n" 830 " extlh %2,%3,%2\n" 831 "3:\n" 832 EXC(1b,3b,%1,%0) 833 EXC(2b,3b,%2,%0) 834 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2) 835 : "r"(va), "0"(0)); 836 if (error) 837 goto give_sigsegv; 838 alpha_write_fp_reg(reg, s_mem_to_reg((int)(tmp1|tmp2))); 839 return; 840 841 case 0x23: /* ldt */ 842 __asm__ __volatile__( 843 "1: ldq_u %1,0(%3)\n" 844 "2: ldq_u %2,7(%3)\n" 845 " extql %1,%3,%1\n" 846 " extqh %2,%3,%2\n" 847 "3:\n" 848 EXC(1b,3b,%1,%0) 849 EXC(2b,3b,%2,%0) 850 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2) 851 : "r"(va), "0"(0)); 852 if (error) 853 goto give_sigsegv; 854 alpha_write_fp_reg(reg, tmp1|tmp2); 855 return; 856 857 case 0x28: /* ldl */ 858 __asm__ __volatile__( 859 "1: ldq_u %1,0(%3)\n" 860 "2: ldq_u %2,3(%3)\n" 861 " extll %1,%3,%1\n" 862 " extlh %2,%3,%2\n" 863 "3:\n" 864 EXC(1b,3b,%1,%0) 865 EXC(2b,3b,%2,%0) 866 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2) 867 : "r"(va), "0"(0)); 868 if (error) 869 goto give_sigsegv; 870 *reg_addr = (int)(tmp1|tmp2); 871 break; 872 873 case 0x29: /* ldq */ 874 __asm__ __volatile__( 875 "1: ldq_u %1,0(%3)\n" 876 "2: ldq_u %2,7(%3)\n" 877 " extql %1,%3,%1\n" 878 " extqh %2,%3,%2\n" 879 "3:\n" 880 EXC(1b,3b,%1,%0) 881 EXC(2b,3b,%2,%0) 882 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2) 883 : "r"(va), "0"(0)); 884 if (error) 885 goto give_sigsegv; 886 *reg_addr = tmp1|tmp2; 887 break; 888 889 /* Note that the store sequences do not indicate that they change 890 memory because it _should_ be affecting nothing in this context. 891 (Otherwise we have other, much larger, problems.) */ 892 case 0x0d: /* stw */ 893 __asm__ __volatile__( 894 "1: ldq_u %2,1(%5)\n" 895 "2: ldq_u %1,0(%5)\n" 896 " inswh %6,%5,%4\n" 897 " inswl %6,%5,%3\n" 898 " mskwh %2,%5,%2\n" 899 " mskwl %1,%5,%1\n" 900 " or %2,%4,%2\n" 901 " or %1,%3,%1\n" 902 "3: stq_u %2,1(%5)\n" 903 "4: stq_u %1,0(%5)\n" 904 "5:\n" 905 EXC(1b,5b,%2,%0) 906 EXC(2b,5b,%1,%0) 907 EXC(3b,5b,$31,%0) 908 EXC(4b,5b,$31,%0) 909 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2), 910 "=&r"(tmp3), "=&r"(tmp4) 911 : "r"(va), "r"(*reg_addr), "0"(0)); 912 if (error) 913 goto give_sigsegv; 914 return; 915 916 case 0x26: /* sts */ 917 fake_reg = s_reg_to_mem(alpha_read_fp_reg(reg)); 918 /* FALLTHRU */ 919 920 case 0x2c: /* stl */ 921 __asm__ __volatile__( 922 "1: ldq_u %2,3(%5)\n" 923 "2: ldq_u %1,0(%5)\n" 924 " inslh %6,%5,%4\n" 925 " insll %6,%5,%3\n" 926 " msklh %2,%5,%2\n" 927 " mskll %1,%5,%1\n" 928 " or %2,%4,%2\n" 929 " or %1,%3,%1\n" 930 "3: stq_u %2,3(%5)\n" 931 "4: stq_u %1,0(%5)\n" 932 "5:\n" 933 EXC(1b,5b,%2,%0) 934 EXC(2b,5b,%1,%0) 935 EXC(3b,5b,$31,%0) 936 EXC(4b,5b,$31,%0) 937 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2), 938 "=&r"(tmp3), "=&r"(tmp4) 939 : "r"(va), "r"(*reg_addr), "0"(0)); 940 if (error) 941 goto give_sigsegv; 942 return; 943 944 case 0x27: /* stt */ 945 fake_reg = alpha_read_fp_reg(reg); 946 /* FALLTHRU */ 947 948 case 0x2d: /* stq */ 949 __asm__ __volatile__( 950 "1: ldq_u %2,7(%5)\n" 951 "2: ldq_u %1,0(%5)\n" 952 " insqh %6,%5,%4\n" 953 " insql %6,%5,%3\n" 954 " mskqh %2,%5,%2\n" 955 " mskql %1,%5,%1\n" 956 " or %2,%4,%2\n" 957 " or %1,%3,%1\n" 958 "3: stq_u %2,7(%5)\n" 959 "4: stq_u %1,0(%5)\n" 960 "5:\n" 961 EXC(1b,5b,%2,%0) 962 EXC(2b,5b,%1,%0) 963 EXC(3b,5b,$31,%0) 964 EXC(4b,5b,$31,%0) 965 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2), 966 "=&r"(tmp3), "=&r"(tmp4) 967 : "r"(va), "r"(*reg_addr), "0"(0)); 968 if (error) 969 goto give_sigsegv; 970 return; 971 972 default: 973 /* What instruction were you trying to use, exactly? */ 974 goto give_sigbus; 975 } 976 977 /* Only integer loads should get here; everyone else returns early. */ 978 if (reg == 30) 979 wrusp(fake_reg); 980 return; 981 982 give_sigsegv: 983 regs->pc -= 4; /* make pc point to faulting insn */ 984 info.si_signo = SIGSEGV; 985 info.si_errno = 0; 986 987 /* We need to replicate some of the logic in mm/fault.c, 988 since we don't have access to the fault code in the 989 exception handling return path. */ 990 if ((unsigned long)va >= TASK_SIZE) 991 info.si_code = SEGV_ACCERR; 992 else { 993 struct mm_struct *mm = current->mm; 994 down_read(&mm->mmap_sem); 995 if (find_vma(mm, (unsigned long)va)) 996 info.si_code = SEGV_ACCERR; 997 else 998 info.si_code = SEGV_MAPERR; 999 up_read(&mm->mmap_sem); 1000 } 1001 info.si_addr = va; 1002 send_sig_info(SIGSEGV, &info, current); 1003 return; 1004 1005 give_sigbus: 1006 regs->pc -= 4; 1007 info.si_signo = SIGBUS; 1008 info.si_errno = 0; 1009 info.si_code = BUS_ADRALN; 1010 info.si_addr = va; 1011 send_sig_info(SIGBUS, &info, current); 1012 return; 1013 } 1014 1015 void 1016 trap_init(void) 1017 { 1018 /* Tell PAL-code what global pointer we want in the kernel. */ 1019 register unsigned long gptr __asm__("$29"); 1020 wrkgp(gptr); 1021 1022 /* Hack for Multia (UDB) and JENSEN: some of their SRMs have 1023 a bug in the handling of the opDEC fault. Fix it up if so. */ 1024 if (implver() == IMPLVER_EV4) 1025 opDEC_check(); 1026 1027 wrent(entArith, 1); 1028 wrent(entMM, 2); 1029 wrent(entIF, 3); 1030 wrent(entUna, 4); 1031 wrent(entSys, 5); 1032 wrent(entDbg, 6); 1033 } 1034