1 /* 2 * linux/arch/alpha/kernel/sys_titan.c 3 * 4 * Copyright (C) 1995 David A Rusling 5 * Copyright (C) 1996, 1999 Jay A Estabrook 6 * Copyright (C) 1998, 1999 Richard Henderson 7 * Copyright (C) 1999, 2000 Jeff Wiedemeier 8 * 9 * Code supporting TITAN systems (EV6+TITAN), currently: 10 * Privateer 11 * Falcon 12 * Granite 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/types.h> 17 #include <linux/mm.h> 18 #include <linux/sched.h> 19 #include <linux/pci.h> 20 #include <linux/init.h> 21 #include <linux/bitops.h> 22 23 #include <asm/ptrace.h> 24 #include <asm/system.h> 25 #include <asm/dma.h> 26 #include <asm/irq.h> 27 #include <asm/mmu_context.h> 28 #include <asm/io.h> 29 #include <asm/pgtable.h> 30 #include <asm/core_titan.h> 31 #include <asm/hwrpb.h> 32 #include <asm/tlbflush.h> 33 34 #include "proto.h" 35 #include "irq_impl.h" 36 #include "pci_impl.h" 37 #include "machvec_impl.h" 38 #include "err_impl.h" 39 40 41 /* 42 * Titan generic 43 */ 44 45 /* 46 * Titan supports up to 4 CPUs 47 */ 48 static unsigned long titan_cpu_irq_affinity[4] = { ~0UL, ~0UL, ~0UL, ~0UL }; 49 50 /* 51 * Mask is set (1) if enabled 52 */ 53 static unsigned long titan_cached_irq_mask; 54 55 /* 56 * Need SMP-safe access to interrupt CSRs 57 */ 58 DEFINE_SPINLOCK(titan_irq_lock); 59 60 static void 61 titan_update_irq_hw(unsigned long mask) 62 { 63 register titan_cchip *cchip = TITAN_cchip; 64 unsigned long isa_enable = 1UL << 55; 65 register int bcpu = boot_cpuid; 66 67 #ifdef CONFIG_SMP 68 cpumask_t cpm; 69 volatile unsigned long *dim0, *dim1, *dim2, *dim3; 70 unsigned long mask0, mask1, mask2, mask3, dummy; 71 72 cpumask_copy(&cpm, cpu_present_mask); 73 mask &= ~isa_enable; 74 mask0 = mask & titan_cpu_irq_affinity[0]; 75 mask1 = mask & titan_cpu_irq_affinity[1]; 76 mask2 = mask & titan_cpu_irq_affinity[2]; 77 mask3 = mask & titan_cpu_irq_affinity[3]; 78 79 if (bcpu == 0) mask0 |= isa_enable; 80 else if (bcpu == 1) mask1 |= isa_enable; 81 else if (bcpu == 2) mask2 |= isa_enable; 82 else mask3 |= isa_enable; 83 84 dim0 = &cchip->dim0.csr; 85 dim1 = &cchip->dim1.csr; 86 dim2 = &cchip->dim2.csr; 87 dim3 = &cchip->dim3.csr; 88 if (!cpumask_test_cpu(0, &cpm)) dim0 = &dummy; 89 if (!cpumask_test_cpu(1, &cpm)) dim1 = &dummy; 90 if (!cpumask_test_cpu(2, &cpm)) dim2 = &dummy; 91 if (!cpumask_test_cpu(3, &cpm)) dim3 = &dummy; 92 93 *dim0 = mask0; 94 *dim1 = mask1; 95 *dim2 = mask2; 96 *dim3 = mask3; 97 mb(); 98 *dim0; 99 *dim1; 100 *dim2; 101 *dim3; 102 #else 103 volatile unsigned long *dimB; 104 dimB = &cchip->dim0.csr; 105 if (bcpu == 1) dimB = &cchip->dim1.csr; 106 else if (bcpu == 2) dimB = &cchip->dim2.csr; 107 else if (bcpu == 3) dimB = &cchip->dim3.csr; 108 109 *dimB = mask | isa_enable; 110 mb(); 111 *dimB; 112 #endif 113 } 114 115 static inline void 116 titan_enable_irq(struct irq_data *d) 117 { 118 unsigned int irq = d->irq; 119 spin_lock(&titan_irq_lock); 120 titan_cached_irq_mask |= 1UL << (irq - 16); 121 titan_update_irq_hw(titan_cached_irq_mask); 122 spin_unlock(&titan_irq_lock); 123 } 124 125 static inline void 126 titan_disable_irq(struct irq_data *d) 127 { 128 unsigned int irq = d->irq; 129 spin_lock(&titan_irq_lock); 130 titan_cached_irq_mask &= ~(1UL << (irq - 16)); 131 titan_update_irq_hw(titan_cached_irq_mask); 132 spin_unlock(&titan_irq_lock); 133 } 134 135 static void 136 titan_cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity) 137 { 138 int cpu; 139 140 for (cpu = 0; cpu < 4; cpu++) { 141 if (cpumask_test_cpu(cpu, &affinity)) 142 titan_cpu_irq_affinity[cpu] |= 1UL << irq; 143 else 144 titan_cpu_irq_affinity[cpu] &= ~(1UL << irq); 145 } 146 147 } 148 149 static int 150 titan_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity, 151 bool force) 152 { 153 unsigned int irq = d->irq; 154 spin_lock(&titan_irq_lock); 155 titan_cpu_set_irq_affinity(irq - 16, *affinity); 156 titan_update_irq_hw(titan_cached_irq_mask); 157 spin_unlock(&titan_irq_lock); 158 159 return 0; 160 } 161 162 static void 163 titan_device_interrupt(unsigned long vector) 164 { 165 printk("titan_device_interrupt: NOT IMPLEMENTED YET!!\n"); 166 } 167 168 static void 169 titan_srm_device_interrupt(unsigned long vector) 170 { 171 int irq; 172 173 irq = (vector - 0x800) >> 4; 174 handle_irq(irq); 175 } 176 177 178 static void __init 179 init_titan_irqs(struct irq_chip * ops, int imin, int imax) 180 { 181 long i; 182 for (i = imin; i <= imax; ++i) { 183 irq_set_chip_and_handler(i, ops, handle_level_irq); 184 irq_set_status_flags(i, IRQ_LEVEL); 185 } 186 } 187 188 static struct irq_chip titan_irq_type = { 189 .name = "TITAN", 190 .irq_unmask = titan_enable_irq, 191 .irq_mask = titan_disable_irq, 192 .irq_mask_ack = titan_disable_irq, 193 .irq_set_affinity = titan_set_irq_affinity, 194 }; 195 196 static irqreturn_t 197 titan_intr_nop(int irq, void *dev_id) 198 { 199 /* 200 * This is a NOP interrupt handler for the purposes of 201 * event counting -- just return. 202 */ 203 return IRQ_HANDLED; 204 } 205 206 static void __init 207 titan_init_irq(void) 208 { 209 if (alpha_using_srm && !alpha_mv.device_interrupt) 210 alpha_mv.device_interrupt = titan_srm_device_interrupt; 211 if (!alpha_mv.device_interrupt) 212 alpha_mv.device_interrupt = titan_device_interrupt; 213 214 titan_update_irq_hw(0); 215 216 init_titan_irqs(&titan_irq_type, 16, 63 + 16); 217 } 218 219 static void __init 220 titan_legacy_init_irq(void) 221 { 222 /* init the legacy dma controller */ 223 outb(0, DMA1_RESET_REG); 224 outb(0, DMA2_RESET_REG); 225 outb(DMA_MODE_CASCADE, DMA2_MODE_REG); 226 outb(0, DMA2_MASK_REG); 227 228 /* init the legacy irq controller */ 229 init_i8259a_irqs(); 230 231 /* init the titan irqs */ 232 titan_init_irq(); 233 } 234 235 void 236 titan_dispatch_irqs(u64 mask) 237 { 238 unsigned long vector; 239 240 /* 241 * Mask down to those interrupts which are enable on this processor 242 */ 243 mask &= titan_cpu_irq_affinity[smp_processor_id()]; 244 245 /* 246 * Dispatch all requested interrupts 247 */ 248 while (mask) { 249 /* convert to SRM vector... priority is <63> -> <0> */ 250 vector = 63 - __kernel_ctlz(mask); 251 mask &= ~(1UL << vector); /* clear it out */ 252 vector = 0x900 + (vector << 4); /* convert to SRM vector */ 253 254 /* dispatch it */ 255 alpha_mv.device_interrupt(vector); 256 } 257 } 258 259 260 /* 261 * Titan Family 262 */ 263 static void __init 264 titan_request_irq(unsigned int irq, irq_handler_t handler, 265 unsigned long irqflags, const char *devname, 266 void *dev_id) 267 { 268 int err; 269 err = request_irq(irq, handler, irqflags, devname, dev_id); 270 if (err) { 271 printk("titan_request_irq for IRQ %d returned %d; ignoring\n", 272 irq, err); 273 } 274 } 275 276 static void __init 277 titan_late_init(void) 278 { 279 /* 280 * Enable the system error interrupts. These interrupts are 281 * all reported to the kernel as machine checks, so the handler 282 * is a nop so it can be called to count the individual events. 283 */ 284 titan_request_irq(63+16, titan_intr_nop, IRQF_DISABLED, 285 "CChip Error", NULL); 286 titan_request_irq(62+16, titan_intr_nop, IRQF_DISABLED, 287 "PChip 0 H_Error", NULL); 288 titan_request_irq(61+16, titan_intr_nop, IRQF_DISABLED, 289 "PChip 1 H_Error", NULL); 290 titan_request_irq(60+16, titan_intr_nop, IRQF_DISABLED, 291 "PChip 0 C_Error", NULL); 292 titan_request_irq(59+16, titan_intr_nop, IRQF_DISABLED, 293 "PChip 1 C_Error", NULL); 294 295 /* 296 * Register our error handlers. 297 */ 298 titan_register_error_handlers(); 299 300 /* 301 * Check if the console left us any error logs. 302 */ 303 cdl_check_console_data_log(); 304 305 } 306 307 static int __devinit 308 titan_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 309 { 310 u8 intline; 311 int irq; 312 313 /* Get the current intline. */ 314 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline); 315 irq = intline; 316 317 /* Is it explicitly routed through ISA? */ 318 if ((irq & 0xF0) == 0xE0) 319 return irq; 320 321 /* Offset by 16 to make room for ISA interrupts 0 - 15. */ 322 return irq + 16; 323 } 324 325 static void __init 326 titan_init_pci(void) 327 { 328 /* 329 * This isn't really the right place, but there's some init 330 * that needs to be done after everything is basically up. 331 */ 332 titan_late_init(); 333 334 pci_probe_only = 1; 335 common_init_pci(); 336 SMC669_Init(0); 337 locate_and_init_vga(NULL); 338 } 339 340 341 /* 342 * Privateer 343 */ 344 static void __init 345 privateer_init_pci(void) 346 { 347 /* 348 * Hook a couple of extra err interrupts that the 349 * common titan code won't. 350 */ 351 titan_request_irq(53+16, titan_intr_nop, IRQF_DISABLED, 352 "NMI", NULL); 353 titan_request_irq(50+16, titan_intr_nop, IRQF_DISABLED, 354 "Temperature Warning", NULL); 355 356 /* 357 * Finish with the common version. 358 */ 359 return titan_init_pci(); 360 } 361 362 363 /* 364 * The System Vectors. 365 */ 366 struct alpha_machine_vector titan_mv __initmv = { 367 .vector_name = "TITAN", 368 DO_EV6_MMU, 369 DO_DEFAULT_RTC, 370 DO_TITAN_IO, 371 .machine_check = titan_machine_check, 372 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 373 .min_io_address = DEFAULT_IO_BASE, 374 .min_mem_address = DEFAULT_MEM_BASE, 375 .pci_dac_offset = TITAN_DAC_OFFSET, 376 377 .nr_irqs = 80, /* 64 + 16 */ 378 /* device_interrupt will be filled in by titan_init_irq */ 379 380 .agp_info = titan_agp_info, 381 382 .init_arch = titan_init_arch, 383 .init_irq = titan_legacy_init_irq, 384 .init_rtc = common_init_rtc, 385 .init_pci = titan_init_pci, 386 387 .kill_arch = titan_kill_arch, 388 .pci_map_irq = titan_map_irq, 389 .pci_swizzle = common_swizzle, 390 }; 391 ALIAS_MV(titan) 392 393 struct alpha_machine_vector privateer_mv __initmv = { 394 .vector_name = "PRIVATEER", 395 DO_EV6_MMU, 396 DO_DEFAULT_RTC, 397 DO_TITAN_IO, 398 .machine_check = privateer_machine_check, 399 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 400 .min_io_address = DEFAULT_IO_BASE, 401 .min_mem_address = DEFAULT_MEM_BASE, 402 .pci_dac_offset = TITAN_DAC_OFFSET, 403 404 .nr_irqs = 80, /* 64 + 16 */ 405 /* device_interrupt will be filled in by titan_init_irq */ 406 407 .agp_info = titan_agp_info, 408 409 .init_arch = titan_init_arch, 410 .init_irq = titan_legacy_init_irq, 411 .init_rtc = common_init_rtc, 412 .init_pci = privateer_init_pci, 413 414 .kill_arch = titan_kill_arch, 415 .pci_map_irq = titan_map_irq, 416 .pci_swizzle = common_swizzle, 417 }; 418 /* No alpha_mv alias for privateer since we compile it 419 in unconditionally with titan; setup_arch knows how to cope. */ 420