1 /* 2 * linux/arch/alpha/kernel/sys_titan.c 3 * 4 * Copyright (C) 1995 David A Rusling 5 * Copyright (C) 1996, 1999 Jay A Estabrook 6 * Copyright (C) 1998, 1999 Richard Henderson 7 * Copyright (C) 1999, 2000 Jeff Wiedemeier 8 * 9 * Code supporting TITAN systems (EV6+TITAN), currently: 10 * Privateer 11 * Falcon 12 * Granite 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/types.h> 17 #include <linux/mm.h> 18 #include <linux/sched.h> 19 #include <linux/pci.h> 20 #include <linux/init.h> 21 #include <linux/bitops.h> 22 23 #include <asm/ptrace.h> 24 #include <asm/system.h> 25 #include <asm/dma.h> 26 #include <asm/irq.h> 27 #include <asm/mmu_context.h> 28 #include <asm/io.h> 29 #include <asm/pgtable.h> 30 #include <asm/core_titan.h> 31 #include <asm/hwrpb.h> 32 #include <asm/tlbflush.h> 33 34 #include "proto.h" 35 #include "irq_impl.h" 36 #include "pci_impl.h" 37 #include "machvec_impl.h" 38 #include "err_impl.h" 39 40 41 /* 42 * Titan generic 43 */ 44 45 /* 46 * Titan supports up to 4 CPUs 47 */ 48 static unsigned long titan_cpu_irq_affinity[4] = { ~0UL, ~0UL, ~0UL, ~0UL }; 49 50 /* 51 * Mask is set (1) if enabled 52 */ 53 static unsigned long titan_cached_irq_mask; 54 55 /* 56 * Need SMP-safe access to interrupt CSRs 57 */ 58 DEFINE_SPINLOCK(titan_irq_lock); 59 60 static void 61 titan_update_irq_hw(unsigned long mask) 62 { 63 register titan_cchip *cchip = TITAN_cchip; 64 unsigned long isa_enable = 1UL << 55; 65 register int bcpu = boot_cpuid; 66 67 #ifdef CONFIG_SMP 68 cpumask_t cpm = cpu_present_map; 69 volatile unsigned long *dim0, *dim1, *dim2, *dim3; 70 unsigned long mask0, mask1, mask2, mask3, dummy; 71 72 mask &= ~isa_enable; 73 mask0 = mask & titan_cpu_irq_affinity[0]; 74 mask1 = mask & titan_cpu_irq_affinity[1]; 75 mask2 = mask & titan_cpu_irq_affinity[2]; 76 mask3 = mask & titan_cpu_irq_affinity[3]; 77 78 if (bcpu == 0) mask0 |= isa_enable; 79 else if (bcpu == 1) mask1 |= isa_enable; 80 else if (bcpu == 2) mask2 |= isa_enable; 81 else mask3 |= isa_enable; 82 83 dim0 = &cchip->dim0.csr; 84 dim1 = &cchip->dim1.csr; 85 dim2 = &cchip->dim2.csr; 86 dim3 = &cchip->dim3.csr; 87 if (!cpu_isset(0, cpm)) dim0 = &dummy; 88 if (!cpu_isset(1, cpm)) dim1 = &dummy; 89 if (!cpu_isset(2, cpm)) dim2 = &dummy; 90 if (!cpu_isset(3, cpm)) dim3 = &dummy; 91 92 *dim0 = mask0; 93 *dim1 = mask1; 94 *dim2 = mask2; 95 *dim3 = mask3; 96 mb(); 97 *dim0; 98 *dim1; 99 *dim2; 100 *dim3; 101 #else 102 volatile unsigned long *dimB; 103 dimB = &cchip->dim0.csr; 104 if (bcpu == 1) dimB = &cchip->dim1.csr; 105 else if (bcpu == 2) dimB = &cchip->dim2.csr; 106 else if (bcpu == 3) dimB = &cchip->dim3.csr; 107 108 *dimB = mask | isa_enable; 109 mb(); 110 *dimB; 111 #endif 112 } 113 114 static inline void 115 titan_enable_irq(unsigned int irq) 116 { 117 spin_lock(&titan_irq_lock); 118 titan_cached_irq_mask |= 1UL << (irq - 16); 119 titan_update_irq_hw(titan_cached_irq_mask); 120 spin_unlock(&titan_irq_lock); 121 } 122 123 static inline void 124 titan_disable_irq(unsigned int irq) 125 { 126 spin_lock(&titan_irq_lock); 127 titan_cached_irq_mask &= ~(1UL << (irq - 16)); 128 titan_update_irq_hw(titan_cached_irq_mask); 129 spin_unlock(&titan_irq_lock); 130 } 131 132 static unsigned int 133 titan_startup_irq(unsigned int irq) 134 { 135 titan_enable_irq(irq); 136 return 0; /* never anything pending */ 137 } 138 139 static void 140 titan_end_irq(unsigned int irq) 141 { 142 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 143 titan_enable_irq(irq); 144 } 145 146 static void 147 titan_cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity) 148 { 149 int cpu; 150 151 for (cpu = 0; cpu < 4; cpu++) { 152 if (cpu_isset(cpu, affinity)) 153 titan_cpu_irq_affinity[cpu] |= 1UL << irq; 154 else 155 titan_cpu_irq_affinity[cpu] &= ~(1UL << irq); 156 } 157 158 } 159 160 static void 161 titan_set_irq_affinity(unsigned int irq, cpumask_t affinity) 162 { 163 spin_lock(&titan_irq_lock); 164 titan_cpu_set_irq_affinity(irq - 16, affinity); 165 titan_update_irq_hw(titan_cached_irq_mask); 166 spin_unlock(&titan_irq_lock); 167 } 168 169 static void 170 titan_device_interrupt(unsigned long vector) 171 { 172 printk("titan_device_interrupt: NOT IMPLEMENTED YET!! \n"); 173 } 174 175 static void 176 titan_srm_device_interrupt(unsigned long vector) 177 { 178 int irq; 179 180 irq = (vector - 0x800) >> 4; 181 handle_irq(irq); 182 } 183 184 185 static void __init 186 init_titan_irqs(struct hw_interrupt_type * ops, int imin, int imax) 187 { 188 long i; 189 for (i = imin; i <= imax; ++i) { 190 irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; 191 irq_desc[i].chip = ops; 192 } 193 } 194 195 static struct hw_interrupt_type titan_irq_type = { 196 .typename = "TITAN", 197 .startup = titan_startup_irq, 198 .shutdown = titan_disable_irq, 199 .enable = titan_enable_irq, 200 .disable = titan_disable_irq, 201 .ack = titan_disable_irq, 202 .end = titan_end_irq, 203 .set_affinity = titan_set_irq_affinity, 204 }; 205 206 static irqreturn_t 207 titan_intr_nop(int irq, void *dev_id, struct pt_regs *regs) 208 { 209 /* 210 * This is a NOP interrupt handler for the purposes of 211 * event counting -- just return. 212 */ 213 return IRQ_HANDLED; 214 } 215 216 static void __init 217 titan_init_irq(void) 218 { 219 if (alpha_using_srm && !alpha_mv.device_interrupt) 220 alpha_mv.device_interrupt = titan_srm_device_interrupt; 221 if (!alpha_mv.device_interrupt) 222 alpha_mv.device_interrupt = titan_device_interrupt; 223 224 titan_update_irq_hw(0); 225 226 init_titan_irqs(&titan_irq_type, 16, 63 + 16); 227 } 228 229 static void __init 230 titan_legacy_init_irq(void) 231 { 232 /* init the legacy dma controller */ 233 outb(0, DMA1_RESET_REG); 234 outb(0, DMA2_RESET_REG); 235 outb(DMA_MODE_CASCADE, DMA2_MODE_REG); 236 outb(0, DMA2_MASK_REG); 237 238 /* init the legacy irq controller */ 239 init_i8259a_irqs(); 240 241 /* init the titan irqs */ 242 titan_init_irq(); 243 } 244 245 void 246 titan_dispatch_irqs(u64 mask, struct pt_regs *regs) 247 { 248 struct pt_regs *old_regs; 249 unsigned long vector; 250 251 /* 252 * Mask down to those interrupts which are enable on this processor 253 */ 254 mask &= titan_cpu_irq_affinity[smp_processor_id()]; 255 256 old_regs = set_irq_regs(regs); 257 /* 258 * Dispatch all requested interrupts 259 */ 260 while (mask) { 261 /* convert to SRM vector... priority is <63> -> <0> */ 262 __asm__("ctlz %1, %0" : "=r"(vector) : "r"(mask)); 263 vector = 63 - vector; 264 mask &= ~(1UL << vector); /* clear it out */ 265 vector = 0x900 + (vector << 4); /* convert to SRM vector */ 266 267 /* dispatch it */ 268 alpha_mv.device_interrupt(vector); 269 } 270 set_irq_regs(old_regs); 271 } 272 273 274 /* 275 * Titan Family 276 */ 277 static void __init 278 titan_late_init(void) 279 { 280 /* 281 * Enable the system error interrupts. These interrupts are 282 * all reported to the kernel as machine checks, so the handler 283 * is a nop so it can be called to count the individual events. 284 */ 285 request_irq(63+16, titan_intr_nop, IRQF_DISABLED, 286 "CChip Error", NULL); 287 request_irq(62+16, titan_intr_nop, IRQF_DISABLED, 288 "PChip 0 H_Error", NULL); 289 request_irq(61+16, titan_intr_nop, IRQF_DISABLED, 290 "PChip 1 H_Error", NULL); 291 request_irq(60+16, titan_intr_nop, IRQF_DISABLED, 292 "PChip 0 C_Error", NULL); 293 request_irq(59+16, titan_intr_nop, IRQF_DISABLED, 294 "PChip 1 C_Error", NULL); 295 296 /* 297 * Register our error handlers. 298 */ 299 titan_register_error_handlers(); 300 301 /* 302 * Check if the console left us any error logs. 303 */ 304 cdl_check_console_data_log(); 305 306 } 307 308 static int __devinit 309 titan_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 310 { 311 u8 intline; 312 int irq; 313 314 /* Get the current intline. */ 315 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline); 316 irq = intline; 317 318 /* Is it explicitly routed through ISA? */ 319 if ((irq & 0xF0) == 0xE0) 320 return irq; 321 322 /* Offset by 16 to make room for ISA interrupts 0 - 15. */ 323 return irq + 16; 324 } 325 326 static void __init 327 titan_init_pci(void) 328 { 329 /* 330 * This isn't really the right place, but there's some init 331 * that needs to be done after everything is basically up. 332 */ 333 titan_late_init(); 334 335 pci_probe_only = 1; 336 common_init_pci(); 337 SMC669_Init(0); 338 #ifdef CONFIG_VGA_HOSE 339 locate_and_init_vga(NULL); 340 #endif 341 } 342 343 344 /* 345 * Privateer 346 */ 347 static void __init 348 privateer_init_pci(void) 349 { 350 /* 351 * Hook a couple of extra err interrupts that the 352 * common titan code won't. 353 */ 354 request_irq(53+16, titan_intr_nop, IRQF_DISABLED, 355 "NMI", NULL); 356 request_irq(50+16, titan_intr_nop, IRQF_DISABLED, 357 "Temperature Warning", NULL); 358 359 /* 360 * Finish with the common version. 361 */ 362 return titan_init_pci(); 363 } 364 365 366 /* 367 * The System Vectors. 368 */ 369 struct alpha_machine_vector titan_mv __initmv = { 370 .vector_name = "TITAN", 371 DO_EV6_MMU, 372 DO_DEFAULT_RTC, 373 DO_TITAN_IO, 374 .machine_check = titan_machine_check, 375 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 376 .min_io_address = DEFAULT_IO_BASE, 377 .min_mem_address = DEFAULT_MEM_BASE, 378 .pci_dac_offset = TITAN_DAC_OFFSET, 379 380 .nr_irqs = 80, /* 64 + 16 */ 381 /* device_interrupt will be filled in by titan_init_irq */ 382 383 .agp_info = titan_agp_info, 384 385 .init_arch = titan_init_arch, 386 .init_irq = titan_legacy_init_irq, 387 .init_rtc = common_init_rtc, 388 .init_pci = titan_init_pci, 389 390 .kill_arch = titan_kill_arch, 391 .pci_map_irq = titan_map_irq, 392 .pci_swizzle = common_swizzle, 393 }; 394 ALIAS_MV(titan) 395 396 struct alpha_machine_vector privateer_mv __initmv = { 397 .vector_name = "PRIVATEER", 398 DO_EV6_MMU, 399 DO_DEFAULT_RTC, 400 DO_TITAN_IO, 401 .machine_check = privateer_machine_check, 402 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 403 .min_io_address = DEFAULT_IO_BASE, 404 .min_mem_address = DEFAULT_MEM_BASE, 405 .pci_dac_offset = TITAN_DAC_OFFSET, 406 407 .nr_irqs = 80, /* 64 + 16 */ 408 /* device_interrupt will be filled in by titan_init_irq */ 409 410 .agp_info = titan_agp_info, 411 412 .init_arch = titan_init_arch, 413 .init_irq = titan_legacy_init_irq, 414 .init_rtc = common_init_rtc, 415 .init_pci = privateer_init_pci, 416 417 .kill_arch = titan_kill_arch, 418 .pci_map_irq = titan_map_irq, 419 .pci_swizzle = common_swizzle, 420 }; 421 /* No alpha_mv alias for privateer since we compile it 422 in unconditionally with titan; setup_arch knows how to cope. */ 423