1 /* 2 * linux/arch/alpha/kernel/sys_rawhide.c 3 * 4 * Copyright (C) 1995 David A Rusling 5 * Copyright (C) 1996 Jay A Estabrook 6 * Copyright (C) 1998, 1999 Richard Henderson 7 * 8 * Code supporting the RAWHIDE. 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/types.h> 13 #include <linux/mm.h> 14 #include <linux/sched.h> 15 #include <linux/pci.h> 16 #include <linux/init.h> 17 18 #include <asm/ptrace.h> 19 #include <asm/system.h> 20 #include <asm/dma.h> 21 #include <asm/irq.h> 22 #include <asm/mmu_context.h> 23 #include <asm/io.h> 24 #include <asm/pgtable.h> 25 #include <asm/core_mcpcia.h> 26 #include <asm/tlbflush.h> 27 28 #include "proto.h" 29 #include "irq_impl.h" 30 #include "pci_impl.h" 31 #include "machvec_impl.h" 32 33 34 /* 35 * HACK ALERT! only the boot cpu is used for interrupts. 36 */ 37 38 39 /* Note mask bit is true for ENABLED irqs. */ 40 41 static unsigned int hose_irq_masks[4] = { 42 0xff0000, 0xfe0000, 0xff0000, 0xff0000 43 }; 44 static unsigned int cached_irq_masks[4]; 45 DEFINE_SPINLOCK(rawhide_irq_lock); 46 47 static inline void 48 rawhide_update_irq_hw(int hose, int mask) 49 { 50 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose)) = mask; 51 mb(); 52 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose)); 53 } 54 55 #define hose_exists(h) \ 56 (((h) < MCPCIA_MAX_HOSES) && (cached_irq_masks[(h)] != 0)) 57 58 static inline void 59 rawhide_enable_irq(unsigned int irq) 60 { 61 unsigned int mask, hose; 62 63 irq -= 16; 64 hose = irq / 24; 65 if (!hose_exists(hose)) /* if hose non-existent, exit */ 66 return; 67 68 irq -= hose * 24; 69 mask = 1 << irq; 70 71 spin_lock(&rawhide_irq_lock); 72 mask |= cached_irq_masks[hose]; 73 cached_irq_masks[hose] = mask; 74 rawhide_update_irq_hw(hose, mask); 75 spin_unlock(&rawhide_irq_lock); 76 } 77 78 static void 79 rawhide_disable_irq(unsigned int irq) 80 { 81 unsigned int mask, hose; 82 83 irq -= 16; 84 hose = irq / 24; 85 if (!hose_exists(hose)) /* if hose non-existent, exit */ 86 return; 87 88 irq -= hose * 24; 89 mask = ~(1 << irq) | hose_irq_masks[hose]; 90 91 spin_lock(&rawhide_irq_lock); 92 mask &= cached_irq_masks[hose]; 93 cached_irq_masks[hose] = mask; 94 rawhide_update_irq_hw(hose, mask); 95 spin_unlock(&rawhide_irq_lock); 96 } 97 98 static void 99 rawhide_mask_and_ack_irq(unsigned int irq) 100 { 101 unsigned int mask, mask1, hose; 102 103 irq -= 16; 104 hose = irq / 24; 105 if (!hose_exists(hose)) /* if hose non-existent, exit */ 106 return; 107 108 irq -= hose * 24; 109 mask1 = 1 << irq; 110 mask = ~mask1 | hose_irq_masks[hose]; 111 112 spin_lock(&rawhide_irq_lock); 113 114 mask &= cached_irq_masks[hose]; 115 cached_irq_masks[hose] = mask; 116 rawhide_update_irq_hw(hose, mask); 117 118 /* Clear the interrupt. */ 119 *(vuip)MCPCIA_INT_REQ(MCPCIA_HOSE2MID(hose)) = mask1; 120 121 spin_unlock(&rawhide_irq_lock); 122 } 123 124 static struct irq_chip rawhide_irq_type = { 125 .name = "RAWHIDE", 126 .unmask = rawhide_enable_irq, 127 .mask = rawhide_disable_irq, 128 .mask_ack = rawhide_mask_and_ack_irq, 129 }; 130 131 static void 132 rawhide_srm_device_interrupt(unsigned long vector) 133 { 134 int irq; 135 136 irq = (vector - 0x800) >> 4; 137 138 /* 139 * The RAWHIDE SRM console reports PCI interrupts with a vector 140 * 0x80 *higher* than one might expect, as PCI IRQ 0 (ie bit 0) 141 * shows up as IRQ 24, etc, etc. We adjust it down by 8 to have 142 * it line up with the actual bit numbers from the REQ registers, 143 * which is how we manage the interrupts/mask. Sigh... 144 * 145 * Also, PCI #1 interrupts are offset some more... :-( 146 */ 147 148 if (irq == 52) { 149 /* SCSI on PCI1 is special. */ 150 irq = 72; 151 } 152 153 /* Adjust by which hose it is from. */ 154 irq -= ((irq + 16) >> 2) & 0x38; 155 156 handle_irq(irq); 157 } 158 159 static void __init 160 rawhide_init_irq(void) 161 { 162 struct pci_controller *hose; 163 long i; 164 165 mcpcia_init_hoses(); 166 167 /* Clear them all; only hoses that exist will be non-zero. */ 168 for (i = 0; i < MCPCIA_MAX_HOSES; i++) cached_irq_masks[i] = 0; 169 170 for (hose = hose_head; hose; hose = hose->next) { 171 unsigned int h = hose->index; 172 unsigned int mask = hose_irq_masks[h]; 173 174 cached_irq_masks[h] = mask; 175 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(h)) = mask; 176 *(vuip)MCPCIA_INT_MASK1(MCPCIA_HOSE2MID(h)) = 0; 177 } 178 179 for (i = 16; i < 128; ++i) { 180 irq_to_desc(i)->status |= IRQ_LEVEL; 181 set_irq_chip_and_handler(i, &rawhide_irq_type, handle_level_irq); 182 } 183 184 init_i8259a_irqs(); 185 common_init_isa_dma(); 186 } 187 188 /* 189 * PCI Fixup configuration. 190 * 191 * Summary @ MCPCIA_PCI0_INT_REQ: 192 * Bit Meaning 193 * 0 Interrupt Line A from slot 2 PCI0 194 * 1 Interrupt Line B from slot 2 PCI0 195 * 2 Interrupt Line C from slot 2 PCI0 196 * 3 Interrupt Line D from slot 2 PCI0 197 * 4 Interrupt Line A from slot 3 PCI0 198 * 5 Interrupt Line B from slot 3 PCI0 199 * 6 Interrupt Line C from slot 3 PCI0 200 * 7 Interrupt Line D from slot 3 PCI0 201 * 8 Interrupt Line A from slot 4 PCI0 202 * 9 Interrupt Line B from slot 4 PCI0 203 * 10 Interrupt Line C from slot 4 PCI0 204 * 11 Interrupt Line D from slot 4 PCI0 205 * 12 Interrupt Line A from slot 5 PCI0 206 * 13 Interrupt Line B from slot 5 PCI0 207 * 14 Interrupt Line C from slot 5 PCI0 208 * 15 Interrupt Line D from slot 5 PCI0 209 * 16 EISA interrupt (PCI 0) or SCSI interrupt (PCI 1) 210 * 17-23 NA 211 * 212 * IdSel 213 * 1 EISA bridge (PCI bus 0 only) 214 * 2 PCI option slot 2 215 * 3 PCI option slot 3 216 * 4 PCI option slot 4 217 * 5 PCI option slot 5 218 * 219 */ 220 221 static int __init 222 rawhide_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 223 { 224 static char irq_tab[5][5] __initdata = { 225 /*INT INTA INTB INTC INTD */ 226 { 16+16, 16+16, 16+16, 16+16, 16+16}, /* IdSel 1 SCSI PCI 1 */ 227 { 16+ 0, 16+ 0, 16+ 1, 16+ 2, 16+ 3}, /* IdSel 2 slot 2 */ 228 { 16+ 4, 16+ 4, 16+ 5, 16+ 6, 16+ 7}, /* IdSel 3 slot 3 */ 229 { 16+ 8, 16+ 8, 16+ 9, 16+10, 16+11}, /* IdSel 4 slot 4 */ 230 { 16+12, 16+12, 16+13, 16+14, 16+15} /* IdSel 5 slot 5 */ 231 }; 232 const long min_idsel = 1, max_idsel = 5, irqs_per_slot = 5; 233 234 struct pci_controller *hose = dev->sysdata; 235 int irq = COMMON_TABLE_LOOKUP; 236 if (irq >= 0) 237 irq += 24 * hose->index; 238 return irq; 239 } 240 241 242 /* 243 * The System Vector 244 */ 245 246 struct alpha_machine_vector rawhide_mv __initmv = { 247 .vector_name = "Rawhide", 248 DO_EV5_MMU, 249 DO_DEFAULT_RTC, 250 DO_MCPCIA_IO, 251 .machine_check = mcpcia_machine_check, 252 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 253 .min_io_address = DEFAULT_IO_BASE, 254 .min_mem_address = MCPCIA_DEFAULT_MEM_BASE, 255 .pci_dac_offset = MCPCIA_DAC_OFFSET, 256 257 .nr_irqs = 128, 258 .device_interrupt = rawhide_srm_device_interrupt, 259 260 .init_arch = mcpcia_init_arch, 261 .init_irq = rawhide_init_irq, 262 .init_rtc = common_init_rtc, 263 .init_pci = common_init_pci, 264 .kill_arch = NULL, 265 .pci_map_irq = rawhide_map_irq, 266 .pci_swizzle = common_swizzle, 267 }; 268 ALIAS_MV(rawhide) 269