1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * linux/arch/alpha/kernel/sys_noritake.c 4 * 5 * Copyright (C) 1995 David A Rusling 6 * Copyright (C) 1996 Jay A Estabrook 7 * Copyright (C) 1998, 1999 Richard Henderson 8 * 9 * Code supporting the NORITAKE (AlphaServer 1000A), 10 * CORELLE (AlphaServer 800), and ALCOR Primo (AlphaStation 600A). 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/types.h> 15 #include <linux/mm.h> 16 #include <linux/sched.h> 17 #include <linux/pci.h> 18 #include <linux/init.h> 19 #include <linux/bitops.h> 20 21 #include <asm/ptrace.h> 22 #include <asm/mce.h> 23 #include <asm/dma.h> 24 #include <asm/irq.h> 25 #include <asm/mmu_context.h> 26 #include <asm/io.h> 27 #include <asm/pgtable.h> 28 #include <asm/core_apecs.h> 29 #include <asm/core_cia.h> 30 #include <asm/tlbflush.h> 31 32 #include "proto.h" 33 #include "irq_impl.h" 34 #include "pci_impl.h" 35 #include "machvec_impl.h" 36 37 /* Note mask bit is true for ENABLED irqs. */ 38 static int cached_irq_mask; 39 40 static inline void 41 noritake_update_irq_hw(int irq, int mask) 42 { 43 int port = 0x54a; 44 if (irq >= 32) { 45 mask >>= 16; 46 port = 0x54c; 47 } 48 outw(mask, port); 49 } 50 51 static void 52 noritake_enable_irq(struct irq_data *d) 53 { 54 noritake_update_irq_hw(d->irq, cached_irq_mask |= 1 << (d->irq - 16)); 55 } 56 57 static void 58 noritake_disable_irq(struct irq_data *d) 59 { 60 noritake_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << (d->irq - 16))); 61 } 62 63 static struct irq_chip noritake_irq_type = { 64 .name = "NORITAKE", 65 .irq_unmask = noritake_enable_irq, 66 .irq_mask = noritake_disable_irq, 67 .irq_mask_ack = noritake_disable_irq, 68 }; 69 70 static void 71 noritake_device_interrupt(unsigned long vector) 72 { 73 unsigned long pld; 74 unsigned int i; 75 76 /* Read the interrupt summary registers of NORITAKE */ 77 pld = (((unsigned long) inw(0x54c) << 32) 78 | ((unsigned long) inw(0x54a) << 16) 79 | ((unsigned long) inb(0xa0) << 8) 80 | inb(0x20)); 81 82 /* 83 * Now for every possible bit set, work through them and call 84 * the appropriate interrupt handler. 85 */ 86 while (pld) { 87 i = ffz(~pld); 88 pld &= pld - 1; /* clear least bit set */ 89 if (i < 16) { 90 isa_device_interrupt(vector); 91 } else { 92 handle_irq(i); 93 } 94 } 95 } 96 97 static void 98 noritake_srm_device_interrupt(unsigned long vector) 99 { 100 int irq; 101 102 irq = (vector - 0x800) >> 4; 103 104 /* 105 * I really hate to do this, too, but the NORITAKE SRM console also 106 * reports PCI vectors *lower* than I expected from the bit numbers 107 * in the documentation. 108 * But I really don't want to change the fixup code for allocation 109 * of IRQs, nor the alpha_irq_mask maintenance stuff, both of which 110 * look nice and clean now. 111 * So, here's this additional grotty hack... :-( 112 */ 113 if (irq >= 16) 114 irq = irq + 1; 115 116 handle_irq(irq); 117 } 118 119 static void __init 120 noritake_init_irq(void) 121 { 122 long i; 123 124 if (alpha_using_srm) 125 alpha_mv.device_interrupt = noritake_srm_device_interrupt; 126 127 outw(0, 0x54a); 128 outw(0, 0x54c); 129 130 for (i = 16; i < 48; ++i) { 131 irq_set_chip_and_handler(i, &noritake_irq_type, 132 handle_level_irq); 133 irq_set_status_flags(i, IRQ_LEVEL); 134 } 135 136 init_i8259a_irqs(); 137 common_init_isa_dma(); 138 } 139 140 141 /* 142 * PCI Fixup configuration. 143 * 144 * Summary @ 0x542, summary register #1: 145 * Bit Meaning 146 * 0 All valid ints from summary regs 2 & 3 147 * 1 QLOGIC ISP1020A SCSI 148 * 2 Interrupt Line A from slot 0 149 * 3 Interrupt Line B from slot 0 150 * 4 Interrupt Line A from slot 1 151 * 5 Interrupt line B from slot 1 152 * 6 Interrupt Line A from slot 2 153 * 7 Interrupt Line B from slot 2 154 * 8 Interrupt Line A from slot 3 155 * 9 Interrupt Line B from slot 3 156 *10 Interrupt Line A from slot 4 157 *11 Interrupt Line B from slot 4 158 *12 Interrupt Line A from slot 5 159 *13 Interrupt Line B from slot 5 160 *14 Interrupt Line A from slot 6 161 *15 Interrupt Line B from slot 6 162 * 163 * Summary @ 0x544, summary register #2: 164 * Bit Meaning 165 * 0 OR of all unmasked ints in SR #2 166 * 1 OR of secondary bus ints 167 * 2 Interrupt Line C from slot 0 168 * 3 Interrupt Line D from slot 0 169 * 4 Interrupt Line C from slot 1 170 * 5 Interrupt line D from slot 1 171 * 6 Interrupt Line C from slot 2 172 * 7 Interrupt Line D from slot 2 173 * 8 Interrupt Line C from slot 3 174 * 9 Interrupt Line D from slot 3 175 *10 Interrupt Line C from slot 4 176 *11 Interrupt Line D from slot 4 177 *12 Interrupt Line C from slot 5 178 *13 Interrupt Line D from slot 5 179 *14 Interrupt Line C from slot 6 180 *15 Interrupt Line D from slot 6 181 * 182 * The device to slot mapping looks like: 183 * 184 * Slot Device 185 * 7 Intel PCI-EISA bridge chip 186 * 8 DEC PCI-PCI bridge chip 187 * 11 PCI on board slot 0 188 * 12 PCI on board slot 1 189 * 13 PCI on board slot 2 190 * 191 * 192 * This two layered interrupt approach means that we allocate IRQ 16 and 193 * above for PCI interrupts. The IRQ relates to which bit the interrupt 194 * comes in on. This makes interrupt processing much easier. 195 */ 196 197 static int 198 noritake_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 199 { 200 static char irq_tab[15][5] = { 201 /*INT INTA INTB INTC INTD */ 202 /* note: IDSELs 16, 17, and 25 are CORELLE only */ 203 { 16+1, 16+1, 16+1, 16+1, 16+1}, /* IdSel 16, QLOGIC */ 204 { -1, -1, -1, -1, -1}, /* IdSel 17, S3 Trio64 */ 205 { -1, -1, -1, -1, -1}, /* IdSel 18, PCEB */ 206 { -1, -1, -1, -1, -1}, /* IdSel 19, PPB */ 207 { -1, -1, -1, -1, -1}, /* IdSel 20, ???? */ 208 { -1, -1, -1, -1, -1}, /* IdSel 21, ???? */ 209 { 16+2, 16+2, 16+3, 32+2, 32+3}, /* IdSel 22, slot 0 */ 210 { 16+4, 16+4, 16+5, 32+4, 32+5}, /* IdSel 23, slot 1 */ 211 { 16+6, 16+6, 16+7, 32+6, 32+7}, /* IdSel 24, slot 2 */ 212 { 16+8, 16+8, 16+9, 32+8, 32+9}, /* IdSel 25, slot 3 */ 213 /* The following 5 are actually on PCI bus 1, which is 214 across the built-in bridge of the NORITAKE only. */ 215 { 16+1, 16+1, 16+1, 16+1, 16+1}, /* IdSel 16, QLOGIC */ 216 { 16+8, 16+8, 16+9, 32+8, 32+9}, /* IdSel 17, slot 3 */ 217 {16+10, 16+10, 16+11, 32+10, 32+11}, /* IdSel 18, slot 4 */ 218 {16+12, 16+12, 16+13, 32+12, 32+13}, /* IdSel 19, slot 5 */ 219 {16+14, 16+14, 16+15, 32+14, 32+15}, /* IdSel 20, slot 6 */ 220 }; 221 const long min_idsel = 5, max_idsel = 19, irqs_per_slot = 5; 222 return COMMON_TABLE_LOOKUP; 223 } 224 225 static u8 226 noritake_swizzle(struct pci_dev *dev, u8 *pinp) 227 { 228 int slot, pin = *pinp; 229 230 if (dev->bus->number == 0) { 231 slot = PCI_SLOT(dev->devfn); 232 } 233 /* Check for the built-in bridge */ 234 else if (PCI_SLOT(dev->bus->self->devfn) == 8) { 235 slot = PCI_SLOT(dev->devfn) + 15; /* WAG! */ 236 } 237 else 238 { 239 /* Must be a card-based bridge. */ 240 do { 241 if (PCI_SLOT(dev->bus->self->devfn) == 8) { 242 slot = PCI_SLOT(dev->devfn) + 15; 243 break; 244 } 245 pin = pci_swizzle_interrupt_pin(dev, pin); 246 247 /* Move up the chain of bridges. */ 248 dev = dev->bus->self; 249 /* Slot of the next bridge. */ 250 slot = PCI_SLOT(dev->devfn); 251 } while (dev->bus->self); 252 } 253 *pinp = pin; 254 return slot; 255 } 256 257 #if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO) 258 static void 259 noritake_apecs_machine_check(unsigned long vector, unsigned long la_ptr) 260 { 261 #define MCHK_NO_DEVSEL 0x205U 262 #define MCHK_NO_TABT 0x204U 263 264 struct el_common *mchk_header; 265 unsigned int code; 266 267 mchk_header = (struct el_common *)la_ptr; 268 269 /* Clear the error before any reporting. */ 270 mb(); 271 mb(); /* magic */ 272 draina(); 273 apecs_pci_clr_err(); 274 wrmces(0x7); 275 mb(); 276 277 code = mchk_header->code; 278 process_mcheck_info(vector, la_ptr, "NORITAKE APECS", 279 (mcheck_expected(0) 280 && (code == MCHK_NO_DEVSEL 281 || code == MCHK_NO_TABT))); 282 } 283 #endif 284 285 286 /* 287 * The System Vectors 288 */ 289 290 #if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO) 291 struct alpha_machine_vector noritake_mv __initmv = { 292 .vector_name = "Noritake", 293 DO_EV4_MMU, 294 DO_DEFAULT_RTC, 295 DO_APECS_IO, 296 .machine_check = noritake_apecs_machine_check, 297 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 298 .min_io_address = EISA_DEFAULT_IO_BASE, 299 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE, 300 301 .nr_irqs = 48, 302 .device_interrupt = noritake_device_interrupt, 303 304 .init_arch = apecs_init_arch, 305 .init_irq = noritake_init_irq, 306 .init_rtc = common_init_rtc, 307 .init_pci = common_init_pci, 308 .pci_map_irq = noritake_map_irq, 309 .pci_swizzle = noritake_swizzle, 310 }; 311 ALIAS_MV(noritake) 312 #endif 313 314 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PRIMO) 315 struct alpha_machine_vector noritake_primo_mv __initmv = { 316 .vector_name = "Noritake-Primo", 317 DO_EV5_MMU, 318 DO_DEFAULT_RTC, 319 DO_CIA_IO, 320 .machine_check = cia_machine_check, 321 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 322 .min_io_address = EISA_DEFAULT_IO_BASE, 323 .min_mem_address = CIA_DEFAULT_MEM_BASE, 324 325 .nr_irqs = 48, 326 .device_interrupt = noritake_device_interrupt, 327 328 .init_arch = cia_init_arch, 329 .init_irq = noritake_init_irq, 330 .init_rtc = common_init_rtc, 331 .init_pci = cia_init_pci, 332 .kill_arch = cia_kill_arch, 333 .pci_map_irq = noritake_map_irq, 334 .pci_swizzle = noritake_swizzle, 335 }; 336 ALIAS_MV(noritake_primo) 337 #endif 338