1 /* 2 * linux/arch/alpha/kernel/sys_nautilus.c 3 * 4 * Copyright (C) 1995 David A Rusling 5 * Copyright (C) 1998 Richard Henderson 6 * Copyright (C) 1999 Alpha Processor, Inc., 7 * (David Daniel, Stig Telfer, Soohoon Lee) 8 * 9 * Code supporting NAUTILUS systems. 10 * 11 * 12 * NAUTILUS has the following I/O features: 13 * 14 * a) Driven by AMD 751 aka IRONGATE (northbridge): 15 * 4 PCI slots 16 * 1 AGP slot 17 * 18 * b) Driven by ALI M1543C (southbridge) 19 * 2 ISA slots 20 * 2 IDE connectors 21 * 1 dual drive capable FDD controller 22 * 2 serial ports 23 * 1 ECP/EPP/SP parallel port 24 * 2 USB ports 25 */ 26 27 #include <linux/kernel.h> 28 #include <linux/types.h> 29 #include <linux/mm.h> 30 #include <linux/sched.h> 31 #include <linux/pci.h> 32 #include <linux/init.h> 33 #include <linux/reboot.h> 34 #include <linux/bootmem.h> 35 #include <linux/bitops.h> 36 37 #include <asm/ptrace.h> 38 #include <asm/dma.h> 39 #include <asm/irq.h> 40 #include <asm/mmu_context.h> 41 #include <asm/io.h> 42 #include <asm/pci.h> 43 #include <asm/pgtable.h> 44 #include <asm/core_irongate.h> 45 #include <asm/hwrpb.h> 46 #include <asm/tlbflush.h> 47 48 #include "proto.h" 49 #include "err_impl.h" 50 #include "irq_impl.h" 51 #include "pci_impl.h" 52 #include "machvec_impl.h" 53 54 55 static void __init 56 nautilus_init_irq(void) 57 { 58 if (alpha_using_srm) { 59 alpha_mv.device_interrupt = srm_device_interrupt; 60 } 61 62 init_i8259a_irqs(); 63 common_init_isa_dma(); 64 } 65 66 static int __init 67 nautilus_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 68 { 69 /* Preserve the IRQ set up by the console. */ 70 71 u8 irq; 72 /* UP1500: AGP INTA is actually routed to IRQ 5, not IRQ 10 as 73 console reports. Check the device id of AGP bridge to distinguish 74 UP1500 from UP1000/1100. Note: 'pin' is 2 due to bridge swizzle. */ 75 if (slot == 1 && pin == 2 && 76 dev->bus->self && dev->bus->self->device == 0x700f) 77 return 5; 78 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 79 return irq; 80 } 81 82 void 83 nautilus_kill_arch(int mode) 84 { 85 struct pci_bus *bus = pci_isa_hose->bus; 86 u32 pmuport; 87 int off; 88 89 switch (mode) { 90 case LINUX_REBOOT_CMD_RESTART: 91 if (! alpha_using_srm) { 92 u8 t8; 93 pci_bus_read_config_byte(bus, 0x38, 0x43, &t8); 94 pci_bus_write_config_byte(bus, 0x38, 0x43, t8 | 0x80); 95 outb(1, 0x92); 96 outb(0, 0x92); 97 /* NOTREACHED */ 98 } 99 break; 100 101 case LINUX_REBOOT_CMD_POWER_OFF: 102 /* Assume M1543C */ 103 off = 0x2000; /* SLP_TYPE = 0, SLP_EN = 1 */ 104 pci_bus_read_config_dword(bus, 0x88, 0x10, &pmuport); 105 if (!pmuport) { 106 /* M1535D/D+ */ 107 off = 0x3400; /* SLP_TYPE = 5, SLP_EN = 1 */ 108 pci_bus_read_config_dword(bus, 0x88, 0xe0, &pmuport); 109 } 110 pmuport &= 0xfffe; 111 outw(0xffff, pmuport); /* Clear pending events. */ 112 outw(off, pmuport + 4); 113 /* NOTREACHED */ 114 break; 115 } 116 } 117 118 /* Perform analysis of a machine check that arrived from the system (NMI) */ 119 120 static void 121 naut_sys_machine_check(unsigned long vector, unsigned long la_ptr, 122 struct pt_regs *regs) 123 { 124 printk("PC %lx RA %lx\n", regs->pc, regs->r26); 125 irongate_pci_clr_err(); 126 } 127 128 /* Machine checks can come from two sources - those on the CPU and those 129 in the system. They are analysed separately but all starts here. */ 130 131 void 132 nautilus_machine_check(unsigned long vector, unsigned long la_ptr) 133 { 134 char *mchk_class; 135 136 /* Now for some analysis. Machine checks fall into two classes -- 137 those picked up by the system, and those picked up by the CPU. 138 Add to that the two levels of severity - correctable or not. */ 139 140 if (vector == SCB_Q_SYSMCHK 141 && ((IRONGATE0->dramms & 0x300) == 0x300)) { 142 unsigned long nmi_ctl; 143 144 /* Clear ALI NMI */ 145 nmi_ctl = inb(0x61); 146 nmi_ctl |= 0x0c; 147 outb(nmi_ctl, 0x61); 148 nmi_ctl &= ~0x0c; 149 outb(nmi_ctl, 0x61); 150 151 /* Write again clears error bits. */ 152 IRONGATE0->stat_cmd = IRONGATE0->stat_cmd & ~0x100; 153 mb(); 154 IRONGATE0->stat_cmd; 155 156 /* Write again clears error bits. */ 157 IRONGATE0->dramms = IRONGATE0->dramms; 158 mb(); 159 IRONGATE0->dramms; 160 161 draina(); 162 wrmces(0x7); 163 mb(); 164 return; 165 } 166 167 if (vector == SCB_Q_SYSERR) 168 mchk_class = "Correctable"; 169 else if (vector == SCB_Q_SYSMCHK) 170 mchk_class = "Fatal"; 171 else { 172 ev6_machine_check(vector, la_ptr); 173 return; 174 } 175 176 printk(KERN_CRIT "NAUTILUS Machine check 0x%lx " 177 "[%s System Machine Check (NMI)]\n", 178 vector, mchk_class); 179 180 naut_sys_machine_check(vector, la_ptr, get_irq_regs()); 181 182 /* Tell the PALcode to clear the machine check */ 183 draina(); 184 wrmces(0x7); 185 mb(); 186 } 187 188 extern void pcibios_claim_one_bus(struct pci_bus *); 189 190 static struct resource irongate_io = { 191 .name = "Irongate PCI IO", 192 .flags = IORESOURCE_IO, 193 }; 194 static struct resource irongate_mem = { 195 .name = "Irongate PCI MEM", 196 .flags = IORESOURCE_MEM, 197 }; 198 199 void __init 200 nautilus_init_pci(void) 201 { 202 struct pci_controller *hose = hose_head; 203 struct pci_bus *bus; 204 struct pci_dev *irongate; 205 unsigned long bus_align, bus_size, pci_mem; 206 unsigned long memtop = max_low_pfn << PAGE_SHIFT; 207 208 /* Scan our single hose. */ 209 bus = pci_scan_bus(0, alpha_mv.pci_ops, hose); 210 hose->bus = bus; 211 pcibios_claim_one_bus(bus); 212 213 irongate = pci_get_bus_and_slot(0, 0); 214 bus->self = irongate; 215 bus->resource[0] = &irongate_io; 216 bus->resource[1] = &irongate_mem; 217 218 pci_bus_size_bridges(bus); 219 220 /* IO port range. */ 221 bus->resource[0]->start = 0; 222 bus->resource[0]->end = 0xffff; 223 224 /* Set up PCI memory range - limit is hardwired to 0xffffffff, 225 base must be at aligned to 16Mb. */ 226 bus_align = bus->resource[1]->start; 227 bus_size = bus->resource[1]->end + 1 - bus_align; 228 if (bus_align < 0x1000000UL) 229 bus_align = 0x1000000UL; 230 231 pci_mem = (0x100000000UL - bus_size) & -bus_align; 232 233 bus->resource[1]->start = pci_mem; 234 bus->resource[1]->end = 0xffffffffUL; 235 if (request_resource(&iomem_resource, bus->resource[1]) < 0) 236 printk(KERN_ERR "Failed to request MEM on hose 0\n"); 237 238 if (pci_mem < memtop) 239 memtop = pci_mem; 240 if (memtop > alpha_mv.min_mem_address) { 241 free_reserved_area(__va(alpha_mv.min_mem_address), 242 __va(memtop), -1, NULL); 243 printk("nautilus_init_pci: %ldk freed\n", 244 (memtop - alpha_mv.min_mem_address) >> 10); 245 } 246 247 if ((IRONGATE0->dev_vendor >> 16) > 0x7006) /* Albacore? */ 248 IRONGATE0->pci_mem = pci_mem; 249 250 pci_bus_assign_resources(bus); 251 252 /* pci_common_swizzle() relies on bus->self being NULL 253 for the root bus, so just clear it. */ 254 bus->self = NULL; 255 pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq); 256 } 257 258 /* 259 * The System Vectors 260 */ 261 262 struct alpha_machine_vector nautilus_mv __initmv = { 263 .vector_name = "Nautilus", 264 DO_EV6_MMU, 265 DO_DEFAULT_RTC, 266 DO_IRONGATE_IO, 267 .machine_check = nautilus_machine_check, 268 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 269 .min_io_address = DEFAULT_IO_BASE, 270 .min_mem_address = IRONGATE_DEFAULT_MEM_BASE, 271 272 .nr_irqs = 16, 273 .device_interrupt = isa_device_interrupt, 274 275 .init_arch = irongate_init_arch, 276 .init_irq = nautilus_init_irq, 277 .init_rtc = common_init_rtc, 278 .init_pci = nautilus_init_pci, 279 .kill_arch = nautilus_kill_arch, 280 .pci_map_irq = nautilus_map_irq, 281 .pci_swizzle = common_swizzle, 282 }; 283 ALIAS_MV(nautilus) 284