1 /* 2 * linux/arch/alpha/kernel/sys_marvel.c 3 * 4 * Marvel / IO7 support 5 */ 6 7 #include <linux/kernel.h> 8 #include <linux/types.h> 9 #include <linux/mm.h> 10 #include <linux/sched.h> 11 #include <linux/pci.h> 12 #include <linux/init.h> 13 #include <linux/bitops.h> 14 15 #include <asm/ptrace.h> 16 #include <asm/system.h> 17 #include <asm/dma.h> 18 #include <asm/irq.h> 19 #include <asm/mmu_context.h> 20 #include <asm/io.h> 21 #include <asm/pgtable.h> 22 #include <asm/core_marvel.h> 23 #include <asm/hwrpb.h> 24 #include <asm/tlbflush.h> 25 #include <asm/vga.h> 26 #include <asm/rtc.h> 27 28 #include "proto.h" 29 #include "err_impl.h" 30 #include "irq_impl.h" 31 #include "pci_impl.h" 32 #include "machvec_impl.h" 33 34 #if NR_IRQS < MARVEL_NR_IRQS 35 # error NR_IRQS < MARVEL_NR_IRQS !!! 36 #endif 37 38 39 /* 40 * Interrupt handling. 41 */ 42 static void 43 io7_device_interrupt(unsigned long vector) 44 { 45 unsigned int pid; 46 unsigned int irq; 47 48 /* 49 * Vector is 0x800 + (interrupt) 50 * 51 * where (interrupt) is: 52 * 53 * ...16|15 14|13 4|3 0 54 * -----+-----+--------+--- 55 * PE | 0 | irq | 0 56 * 57 * where (irq) is 58 * 59 * 0x0800 - 0x0ff0 - 0x0800 + (LSI id << 4) 60 * 0x1000 - 0x2ff0 - 0x1000 + (MSI_DAT<8:0> << 4) 61 */ 62 pid = vector >> 16; 63 irq = ((vector & 0xffff) - 0x800) >> 4; 64 65 irq += 16; /* offset for legacy */ 66 irq &= MARVEL_IRQ_VEC_IRQ_MASK; /* not too many bits */ 67 irq |= pid << MARVEL_IRQ_VEC_PE_SHIFT; /* merge the pid */ 68 69 handle_irq(irq); 70 } 71 72 static volatile unsigned long * 73 io7_get_irq_ctl(unsigned int irq, struct io7 **pio7) 74 { 75 volatile unsigned long *ctl; 76 unsigned int pid; 77 struct io7 *io7; 78 79 pid = irq >> MARVEL_IRQ_VEC_PE_SHIFT; 80 81 if (!(io7 = marvel_find_io7(pid))) { 82 printk(KERN_ERR 83 "%s for nonexistent io7 -- vec %x, pid %d\n", 84 __func__, irq, pid); 85 return NULL; 86 } 87 88 irq &= MARVEL_IRQ_VEC_IRQ_MASK; /* isolate the vector */ 89 irq -= 16; /* subtract legacy bias */ 90 91 if (irq >= 0x180) { 92 printk(KERN_ERR 93 "%s for invalid irq -- pid %d adjusted irq %x\n", 94 __func__, pid, irq); 95 return NULL; 96 } 97 98 ctl = &io7->csrs->PO7_LSI_CTL[irq & 0xff].csr; /* assume LSI */ 99 if (irq >= 0x80) /* MSI */ 100 ctl = &io7->csrs->PO7_MSI_CTL[((irq - 0x80) >> 5) & 0x0f].csr; 101 102 if (pio7) *pio7 = io7; 103 return ctl; 104 } 105 106 static void 107 io7_enable_irq(unsigned int irq) 108 { 109 volatile unsigned long *ctl; 110 struct io7 *io7; 111 112 ctl = io7_get_irq_ctl(irq, &io7); 113 if (!ctl || !io7) { 114 printk(KERN_ERR "%s: get_ctl failed for irq %x\n", 115 __func__, irq); 116 return; 117 } 118 119 spin_lock(&io7->irq_lock); 120 *ctl |= 1UL << 24; 121 mb(); 122 *ctl; 123 spin_unlock(&io7->irq_lock); 124 } 125 126 static void 127 io7_disable_irq(unsigned int irq) 128 { 129 volatile unsigned long *ctl; 130 struct io7 *io7; 131 132 ctl = io7_get_irq_ctl(irq, &io7); 133 if (!ctl || !io7) { 134 printk(KERN_ERR "%s: get_ctl failed for irq %x\n", 135 __func__, irq); 136 return; 137 } 138 139 spin_lock(&io7->irq_lock); 140 *ctl &= ~(1UL << 24); 141 mb(); 142 *ctl; 143 spin_unlock(&io7->irq_lock); 144 } 145 146 static void 147 marvel_irq_noop(unsigned int irq) 148 { 149 return; 150 } 151 152 static unsigned int 153 marvel_irq_noop_return(unsigned int irq) 154 { 155 return 0; 156 } 157 158 static struct irq_chip marvel_legacy_irq_type = { 159 .name = "LEGACY", 160 .mask = marvel_irq_noop, 161 .unmask = marvel_irq_noop, 162 }; 163 164 static struct irq_chip io7_lsi_irq_type = { 165 .name = "LSI", 166 .unmask = io7_enable_irq, 167 .mask = io7_disable_irq, 168 .mask_ack = io7_disable_irq, 169 }; 170 171 static struct irq_chip io7_msi_irq_type = { 172 .name = "MSI", 173 .unmask = io7_enable_irq, 174 .mask = io7_disable_irq, 175 .ack = marvel_irq_noop, 176 }; 177 178 static void 179 io7_redirect_irq(struct io7 *io7, 180 volatile unsigned long *csr, 181 unsigned int where) 182 { 183 unsigned long val; 184 185 val = *csr; 186 val &= ~(0x1ffUL << 24); /* clear the target pid */ 187 val |= ((unsigned long)where << 24); /* set the new target pid */ 188 189 *csr = val; 190 mb(); 191 *csr; 192 } 193 194 static void 195 io7_redirect_one_lsi(struct io7 *io7, unsigned int which, unsigned int where) 196 { 197 unsigned long val; 198 199 /* 200 * LSI_CTL has target PID @ 14 201 */ 202 val = io7->csrs->PO7_LSI_CTL[which].csr; 203 val &= ~(0x1ffUL << 14); /* clear the target pid */ 204 val |= ((unsigned long)where << 14); /* set the new target pid */ 205 206 io7->csrs->PO7_LSI_CTL[which].csr = val; 207 mb(); 208 io7->csrs->PO7_LSI_CTL[which].csr; 209 } 210 211 static void 212 io7_redirect_one_msi(struct io7 *io7, unsigned int which, unsigned int where) 213 { 214 unsigned long val; 215 216 /* 217 * MSI_CTL has target PID @ 14 218 */ 219 val = io7->csrs->PO7_MSI_CTL[which].csr; 220 val &= ~(0x1ffUL << 14); /* clear the target pid */ 221 val |= ((unsigned long)where << 14); /* set the new target pid */ 222 223 io7->csrs->PO7_MSI_CTL[which].csr = val; 224 mb(); 225 io7->csrs->PO7_MSI_CTL[which].csr; 226 } 227 228 static void __init 229 init_one_io7_lsi(struct io7 *io7, unsigned int which, unsigned int where) 230 { 231 /* 232 * LSI_CTL has target PID @ 14 233 */ 234 io7->csrs->PO7_LSI_CTL[which].csr = ((unsigned long)where << 14); 235 mb(); 236 io7->csrs->PO7_LSI_CTL[which].csr; 237 } 238 239 static void __init 240 init_one_io7_msi(struct io7 *io7, unsigned int which, unsigned int where) 241 { 242 /* 243 * MSI_CTL has target PID @ 14 244 */ 245 io7->csrs->PO7_MSI_CTL[which].csr = ((unsigned long)where << 14); 246 mb(); 247 io7->csrs->PO7_MSI_CTL[which].csr; 248 } 249 250 static void __init 251 init_io7_irqs(struct io7 *io7, 252 struct irq_chip *lsi_ops, 253 struct irq_chip *msi_ops) 254 { 255 long base = (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT) + 16; 256 long i; 257 258 printk("Initializing interrupts for IO7 at PE %u - base %lx\n", 259 io7->pe, base); 260 261 /* 262 * Where should interrupts from this IO7 go? 263 * 264 * They really should be sent to the local CPU to avoid having to 265 * traverse the mesh, but if it's not an SMP kernel, they have to 266 * go to the boot CPU. Send them all to the boot CPU for now, 267 * as each secondary starts, it can redirect it's local device 268 * interrupts. 269 */ 270 printk(" Interrupts reported to CPU at PE %u\n", boot_cpuid); 271 272 spin_lock(&io7->irq_lock); 273 274 /* set up the error irqs */ 275 io7_redirect_irq(io7, &io7->csrs->HLT_CTL.csr, boot_cpuid); 276 io7_redirect_irq(io7, &io7->csrs->HPI_CTL.csr, boot_cpuid); 277 io7_redirect_irq(io7, &io7->csrs->CRD_CTL.csr, boot_cpuid); 278 io7_redirect_irq(io7, &io7->csrs->STV_CTL.csr, boot_cpuid); 279 io7_redirect_irq(io7, &io7->csrs->HEI_CTL.csr, boot_cpuid); 280 281 /* Set up the lsi irqs. */ 282 for (i = 0; i < 128; ++i) { 283 irq_to_desc(base + i)->status |= IRQ_LEVEL; 284 set_irq_chip_and_handler(base + i, lsi_ops, handle_level_irq); 285 } 286 287 /* Disable the implemented irqs in hardware. */ 288 for (i = 0; i < 0x60; ++i) 289 init_one_io7_lsi(io7, i, boot_cpuid); 290 291 init_one_io7_lsi(io7, 0x74, boot_cpuid); 292 init_one_io7_lsi(io7, 0x75, boot_cpuid); 293 294 295 /* Set up the msi irqs. */ 296 for (i = 128; i < (128 + 512); ++i) { 297 irq_to_desc(base + i)->status |= IRQ_LEVEL; 298 set_irq_chip_and_handler(base + i, msi_ops, handle_level_irq); 299 } 300 301 for (i = 0; i < 16; ++i) 302 init_one_io7_msi(io7, i, boot_cpuid); 303 304 spin_unlock(&io7->irq_lock); 305 } 306 307 static void __init 308 marvel_init_irq(void) 309 { 310 int i; 311 struct io7 *io7 = NULL; 312 313 /* Reserve the legacy irqs. */ 314 for (i = 0; i < 16; ++i) { 315 set_irq_chip_and_handler(i, &marvel_legacy_irq_type, 316 handle_level_irq); 317 } 318 319 /* Init the io7 irqs. */ 320 for (io7 = NULL; (io7 = marvel_next_io7(io7)) != NULL; ) 321 init_io7_irqs(io7, &io7_lsi_irq_type, &io7_msi_irq_type); 322 } 323 324 static int 325 marvel_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 326 { 327 struct pci_controller *hose = dev->sysdata; 328 struct io7_port *io7_port = hose->sysdata; 329 struct io7 *io7 = io7_port->io7; 330 int msi_loc, msi_data_off; 331 u16 msg_ctl; 332 u16 msg_dat; 333 u8 intline; 334 int irq; 335 336 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline); 337 irq = intline; 338 339 msi_loc = pci_find_capability(dev, PCI_CAP_ID_MSI); 340 msg_ctl = 0; 341 if (msi_loc) 342 pci_read_config_word(dev, msi_loc + PCI_MSI_FLAGS, &msg_ctl); 343 344 if (msg_ctl & PCI_MSI_FLAGS_ENABLE) { 345 msi_data_off = PCI_MSI_DATA_32; 346 if (msg_ctl & PCI_MSI_FLAGS_64BIT) 347 msi_data_off = PCI_MSI_DATA_64; 348 pci_read_config_word(dev, msi_loc + msi_data_off, &msg_dat); 349 350 irq = msg_dat & 0x1ff; /* we use msg_data<8:0> */ 351 irq += 0x80; /* offset for lsi */ 352 353 #if 1 354 printk("PCI:%d:%d:%d (hose %d) is using MSI\n", 355 dev->bus->number, 356 PCI_SLOT(dev->devfn), 357 PCI_FUNC(dev->devfn), 358 hose->index); 359 printk(" %d message(s) from 0x%04x\n", 360 1 << ((msg_ctl & PCI_MSI_FLAGS_QSIZE) >> 4), 361 msg_dat); 362 printk(" reporting on %d IRQ(s) from %d (0x%x)\n", 363 1 << ((msg_ctl & PCI_MSI_FLAGS_QSIZE) >> 4), 364 (irq + 16) | (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT), 365 (irq + 16) | (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT)); 366 #endif 367 368 #if 0 369 pci_write_config_word(dev, msi_loc + PCI_MSI_FLAGS, 370 msg_ctl & ~PCI_MSI_FLAGS_ENABLE); 371 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline); 372 irq = intline; 373 374 printk(" forcing LSI interrupt on irq %d [0x%x]\n", irq, irq); 375 #endif 376 } 377 378 irq += 16; /* offset for legacy */ 379 irq |= io7->pe << MARVEL_IRQ_VEC_PE_SHIFT; /* merge the pid */ 380 381 return irq; 382 } 383 384 static void __init 385 marvel_init_pci(void) 386 { 387 struct io7 *io7; 388 389 marvel_register_error_handlers(); 390 391 pci_probe_only = 1; 392 common_init_pci(); 393 locate_and_init_vga(NULL); 394 395 /* Clear any io7 errors. */ 396 for (io7 = NULL; (io7 = marvel_next_io7(io7)) != NULL; ) 397 io7_clear_errors(io7); 398 } 399 400 static void __init 401 marvel_init_rtc(void) 402 { 403 init_rtc_irq(); 404 } 405 406 struct marvel_rtc_time { 407 struct rtc_time *time; 408 int retval; 409 }; 410 411 #ifdef CONFIG_SMP 412 static void 413 smp_get_rtc_time(void *data) 414 { 415 struct marvel_rtc_time *mrt = data; 416 mrt->retval = __get_rtc_time(mrt->time); 417 } 418 419 static void 420 smp_set_rtc_time(void *data) 421 { 422 struct marvel_rtc_time *mrt = data; 423 mrt->retval = __set_rtc_time(mrt->time); 424 } 425 #endif 426 427 static unsigned int 428 marvel_get_rtc_time(struct rtc_time *time) 429 { 430 #ifdef CONFIG_SMP 431 struct marvel_rtc_time mrt; 432 433 if (smp_processor_id() != boot_cpuid) { 434 mrt.time = time; 435 smp_call_function_single(boot_cpuid, smp_get_rtc_time, &mrt, 1); 436 return mrt.retval; 437 } 438 #endif 439 return __get_rtc_time(time); 440 } 441 442 static int 443 marvel_set_rtc_time(struct rtc_time *time) 444 { 445 #ifdef CONFIG_SMP 446 struct marvel_rtc_time mrt; 447 448 if (smp_processor_id() != boot_cpuid) { 449 mrt.time = time; 450 smp_call_function_single(boot_cpuid, smp_set_rtc_time, &mrt, 1); 451 return mrt.retval; 452 } 453 #endif 454 return __set_rtc_time(time); 455 } 456 457 static void 458 marvel_smp_callin(void) 459 { 460 int cpuid = hard_smp_processor_id(); 461 struct io7 *io7 = marvel_find_io7(cpuid); 462 unsigned int i; 463 464 if (!io7) 465 return; 466 467 /* 468 * There is a local IO7 - redirect all of its interrupts here. 469 */ 470 printk("Redirecting IO7 interrupts to local CPU at PE %u\n", cpuid); 471 472 /* Redirect the error IRQS here. */ 473 io7_redirect_irq(io7, &io7->csrs->HLT_CTL.csr, cpuid); 474 io7_redirect_irq(io7, &io7->csrs->HPI_CTL.csr, cpuid); 475 io7_redirect_irq(io7, &io7->csrs->CRD_CTL.csr, cpuid); 476 io7_redirect_irq(io7, &io7->csrs->STV_CTL.csr, cpuid); 477 io7_redirect_irq(io7, &io7->csrs->HEI_CTL.csr, cpuid); 478 479 /* Redirect the implemented LSIs here. */ 480 for (i = 0; i < 0x60; ++i) 481 io7_redirect_one_lsi(io7, i, cpuid); 482 483 io7_redirect_one_lsi(io7, 0x74, cpuid); 484 io7_redirect_one_lsi(io7, 0x75, cpuid); 485 486 /* Redirect the MSIs here. */ 487 for (i = 0; i < 16; ++i) 488 io7_redirect_one_msi(io7, i, cpuid); 489 } 490 491 /* 492 * System Vectors 493 */ 494 struct alpha_machine_vector marvel_ev7_mv __initmv = { 495 .vector_name = "MARVEL/EV7", 496 DO_EV7_MMU, 497 .rtc_port = 0x70, 498 .rtc_get_time = marvel_get_rtc_time, 499 .rtc_set_time = marvel_set_rtc_time, 500 DO_MARVEL_IO, 501 .machine_check = marvel_machine_check, 502 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 503 .min_io_address = DEFAULT_IO_BASE, 504 .min_mem_address = DEFAULT_MEM_BASE, 505 .pci_dac_offset = IO7_DAC_OFFSET, 506 507 .nr_irqs = MARVEL_NR_IRQS, 508 .device_interrupt = io7_device_interrupt, 509 510 .agp_info = marvel_agp_info, 511 512 .smp_callin = marvel_smp_callin, 513 .init_arch = marvel_init_arch, 514 .init_irq = marvel_init_irq, 515 .init_rtc = marvel_init_rtc, 516 .init_pci = marvel_init_pci, 517 .kill_arch = marvel_kill_arch, 518 .pci_map_irq = marvel_map_irq, 519 .pci_swizzle = common_swizzle, 520 521 .pa_to_nid = marvel_pa_to_nid, 522 .cpuid_to_nid = marvel_cpuid_to_nid, 523 .node_mem_start = marvel_node_mem_start, 524 .node_mem_size = marvel_node_mem_size, 525 }; 526 ALIAS_MV(marvel_ev7) 527