1b2441318SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0
21da177e4SLinus Torvalds /*
31da177e4SLinus Torvalds * linux/arch/alpha/kernel/sys_eiger.c
41da177e4SLinus Torvalds *
51da177e4SLinus Torvalds * Copyright (C) 1995 David A Rusling
61da177e4SLinus Torvalds * Copyright (C) 1996, 1999 Jay A Estabrook
71da177e4SLinus Torvalds * Copyright (C) 1998, 1999 Richard Henderson
81da177e4SLinus Torvalds * Copyright (C) 1999 Iain Grant
91da177e4SLinus Torvalds *
101da177e4SLinus Torvalds * Code supporting the EIGER (EV6+TSUNAMI).
111da177e4SLinus Torvalds */
121da177e4SLinus Torvalds
131da177e4SLinus Torvalds #include <linux/kernel.h>
141da177e4SLinus Torvalds #include <linux/types.h>
151da177e4SLinus Torvalds #include <linux/mm.h>
161da177e4SLinus Torvalds #include <linux/sched.h>
171da177e4SLinus Torvalds #include <linux/pci.h>
181da177e4SLinus Torvalds #include <linux/init.h>
191da177e4SLinus Torvalds #include <linux/bitops.h>
201da177e4SLinus Torvalds
211da177e4SLinus Torvalds #include <asm/ptrace.h>
221da177e4SLinus Torvalds #include <asm/dma.h>
231da177e4SLinus Torvalds #include <asm/irq.h>
241da177e4SLinus Torvalds #include <asm/mmu_context.h>
251da177e4SLinus Torvalds #include <asm/io.h>
261da177e4SLinus Torvalds #include <asm/core_tsunami.h>
271da177e4SLinus Torvalds #include <asm/hwrpb.h>
281da177e4SLinus Torvalds #include <asm/tlbflush.h>
291da177e4SLinus Torvalds
301da177e4SLinus Torvalds #include "proto.h"
311da177e4SLinus Torvalds #include "irq_impl.h"
321da177e4SLinus Torvalds #include "pci_impl.h"
331da177e4SLinus Torvalds #include "machvec_impl.h"
341da177e4SLinus Torvalds
351da177e4SLinus Torvalds
361da177e4SLinus Torvalds /* Note that this interrupt code is identical to TAKARA. */
371da177e4SLinus Torvalds
381da177e4SLinus Torvalds /* Note mask bit is true for DISABLED irqs. */
391da177e4SLinus Torvalds static unsigned long cached_irq_mask[2] = { -1, -1 };
401da177e4SLinus Torvalds
411da177e4SLinus Torvalds static inline void
eiger_update_irq_hw(unsigned long irq,unsigned long mask)421da177e4SLinus Torvalds eiger_update_irq_hw(unsigned long irq, unsigned long mask)
431da177e4SLinus Torvalds {
441da177e4SLinus Torvalds int regaddr;
451da177e4SLinus Torvalds
461da177e4SLinus Torvalds mask = (irq >= 64 ? mask << 16 : mask >> ((irq - 16) & 0x30));
471da177e4SLinus Torvalds regaddr = 0x510 + (((irq - 16) >> 2) & 0x0c);
481da177e4SLinus Torvalds outl(mask & 0xffff0000UL, regaddr);
491da177e4SLinus Torvalds }
501da177e4SLinus Torvalds
511da177e4SLinus Torvalds static inline void
eiger_enable_irq(struct irq_data * d)52c0497664SThomas Gleixner eiger_enable_irq(struct irq_data *d)
531da177e4SLinus Torvalds {
54c0497664SThomas Gleixner unsigned int irq = d->irq;
551da177e4SLinus Torvalds unsigned long mask;
561da177e4SLinus Torvalds mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63)));
571da177e4SLinus Torvalds eiger_update_irq_hw(irq, mask);
581da177e4SLinus Torvalds }
591da177e4SLinus Torvalds
601da177e4SLinus Torvalds static void
eiger_disable_irq(struct irq_data * d)61c0497664SThomas Gleixner eiger_disable_irq(struct irq_data *d)
621da177e4SLinus Torvalds {
63c0497664SThomas Gleixner unsigned int irq = d->irq;
641da177e4SLinus Torvalds unsigned long mask;
651da177e4SLinus Torvalds mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63));
661da177e4SLinus Torvalds eiger_update_irq_hw(irq, mask);
671da177e4SLinus Torvalds }
681da177e4SLinus Torvalds
6944377f62SThomas Gleixner static struct irq_chip eiger_irq_type = {
708ab1221cSThomas Gleixner .name = "EIGER",
71c0497664SThomas Gleixner .irq_unmask = eiger_enable_irq,
72c0497664SThomas Gleixner .irq_mask = eiger_disable_irq,
73c0497664SThomas Gleixner .irq_mask_ack = eiger_disable_irq,
741da177e4SLinus Torvalds };
751da177e4SLinus Torvalds
761da177e4SLinus Torvalds static void
eiger_device_interrupt(unsigned long vector)777ca56053SAl Viro eiger_device_interrupt(unsigned long vector)
781da177e4SLinus Torvalds {
791da177e4SLinus Torvalds unsigned intstatus;
801da177e4SLinus Torvalds
811da177e4SLinus Torvalds /*
821da177e4SLinus Torvalds * The PALcode will have passed us vectors 0x800 or 0x810,
831da177e4SLinus Torvalds * which are fairly arbitrary values and serve only to tell
841da177e4SLinus Torvalds * us whether an interrupt has come in on IRQ0 or IRQ1. If
851da177e4SLinus Torvalds * it's IRQ1 it's a PCI interrupt; if it's IRQ0, it's
861da177e4SLinus Torvalds * probably ISA, but PCI interrupts can come through IRQ0
871da177e4SLinus Torvalds * as well if the interrupt controller isn't in accelerated
881da177e4SLinus Torvalds * mode.
891da177e4SLinus Torvalds *
901da177e4SLinus Torvalds * OTOH, the accelerator thing doesn't seem to be working
911da177e4SLinus Torvalds * overly well, so what we'll do instead is try directly
921da177e4SLinus Torvalds * examining the Master Interrupt Register to see if it's a
931da177e4SLinus Torvalds * PCI interrupt, and if _not_ then we'll pass it on to the
941da177e4SLinus Torvalds * ISA handler.
951da177e4SLinus Torvalds */
961da177e4SLinus Torvalds
971da177e4SLinus Torvalds intstatus = inw(0x500) & 15;
981da177e4SLinus Torvalds if (intstatus) {
991da177e4SLinus Torvalds /*
1001da177e4SLinus Torvalds * This is a PCI interrupt. Check each bit and
1011da177e4SLinus Torvalds * despatch an interrupt if it's set.
1021da177e4SLinus Torvalds */
1031da177e4SLinus Torvalds
1043dbb8c62SAl Viro if (intstatus & 8) handle_irq(16+3);
1053dbb8c62SAl Viro if (intstatus & 4) handle_irq(16+2);
1063dbb8c62SAl Viro if (intstatus & 2) handle_irq(16+1);
1073dbb8c62SAl Viro if (intstatus & 1) handle_irq(16+0);
1081da177e4SLinus Torvalds } else {
1097ca56053SAl Viro isa_device_interrupt(vector);
1101da177e4SLinus Torvalds }
1111da177e4SLinus Torvalds }
1121da177e4SLinus Torvalds
1131da177e4SLinus Torvalds static void
eiger_srm_device_interrupt(unsigned long vector)1147ca56053SAl Viro eiger_srm_device_interrupt(unsigned long vector)
1151da177e4SLinus Torvalds {
1161da177e4SLinus Torvalds int irq = (vector - 0x800) >> 4;
1173dbb8c62SAl Viro handle_irq(irq);
1181da177e4SLinus Torvalds }
1191da177e4SLinus Torvalds
1201da177e4SLinus Torvalds static void __init
eiger_init_irq(void)1211da177e4SLinus Torvalds eiger_init_irq(void)
1221da177e4SLinus Torvalds {
1231da177e4SLinus Torvalds long i;
1241da177e4SLinus Torvalds
1251da177e4SLinus Torvalds outb(0, DMA1_RESET_REG);
1261da177e4SLinus Torvalds outb(0, DMA2_RESET_REG);
1271da177e4SLinus Torvalds outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
1281da177e4SLinus Torvalds outb(0, DMA2_MASK_REG);
1291da177e4SLinus Torvalds
1301da177e4SLinus Torvalds if (alpha_using_srm)
1311da177e4SLinus Torvalds alpha_mv.device_interrupt = eiger_srm_device_interrupt;
1321da177e4SLinus Torvalds
1331da177e4SLinus Torvalds for (i = 16; i < 128; i += 16)
1341da177e4SLinus Torvalds eiger_update_irq_hw(i, -1);
1351da177e4SLinus Torvalds
1361da177e4SLinus Torvalds init_i8259a_irqs();
1371da177e4SLinus Torvalds
1381da177e4SLinus Torvalds for (i = 16; i < 128; ++i) {
139a9eb076bSThomas Gleixner irq_set_chip_and_handler(i, &eiger_irq_type, handle_level_irq);
140c0497664SThomas Gleixner irq_set_status_flags(i, IRQ_LEVEL);
1411da177e4SLinus Torvalds }
1421da177e4SLinus Torvalds }
1431da177e4SLinus Torvalds
144814eae59SLorenzo Pieralisi static int
eiger_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)145d5341942SRalf Baechle eiger_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
1461da177e4SLinus Torvalds {
1471da177e4SLinus Torvalds u8 irq_orig;
1481da177e4SLinus Torvalds
1491da177e4SLinus Torvalds /* The SRM console has already calculated out the IRQ value's for
1501da177e4SLinus Torvalds option cards. As this works lets just read in the value already
1511da177e4SLinus Torvalds set and change it to a useable value by Linux.
1521da177e4SLinus Torvalds
1531da177e4SLinus Torvalds All the IRQ values generated by the console are greater than 90,
1541da177e4SLinus Torvalds so we subtract 80 because it is (90 - allocated ISA IRQ's). */
1551da177e4SLinus Torvalds
1561da177e4SLinus Torvalds pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq_orig);
1571da177e4SLinus Torvalds
1581da177e4SLinus Torvalds return irq_orig - 0x80;
1591da177e4SLinus Torvalds }
1601da177e4SLinus Torvalds
161814eae59SLorenzo Pieralisi static u8
eiger_swizzle(struct pci_dev * dev,u8 * pinp)1621da177e4SLinus Torvalds eiger_swizzle(struct pci_dev *dev, u8 *pinp)
1631da177e4SLinus Torvalds {
1641da177e4SLinus Torvalds struct pci_controller *hose = dev->sysdata;
1651da177e4SLinus Torvalds int slot, pin = *pinp;
1661da177e4SLinus Torvalds int bridge_count = 0;
1671da177e4SLinus Torvalds
1681da177e4SLinus Torvalds /* Find the number of backplane bridges. */
1691da177e4SLinus Torvalds int backplane = inw(0x502) & 0x0f;
1701da177e4SLinus Torvalds
1711da177e4SLinus Torvalds switch (backplane)
1721da177e4SLinus Torvalds {
1731da177e4SLinus Torvalds case 0x00: bridge_count = 0; break; /* No bridges */
1741da177e4SLinus Torvalds case 0x01: bridge_count = 1; break; /* 1 */
1751da177e4SLinus Torvalds case 0x03: bridge_count = 2; break; /* 2 */
1761da177e4SLinus Torvalds case 0x07: bridge_count = 3; break; /* 3 */
1771da177e4SLinus Torvalds case 0x0f: bridge_count = 4; break; /* 4 */
178c0ebf715SJason Yan }
1791da177e4SLinus Torvalds
1801da177e4SLinus Torvalds slot = PCI_SLOT(dev->devfn);
1811da177e4SLinus Torvalds while (dev->bus->self) {
1821da177e4SLinus Torvalds /* Check for built-in bridges on hose 0. */
1831da177e4SLinus Torvalds if (hose->index == 0
1841da177e4SLinus Torvalds && (PCI_SLOT(dev->bus->self->devfn)
1851da177e4SLinus Torvalds > 20 - bridge_count)) {
1861da177e4SLinus Torvalds slot = PCI_SLOT(dev->devfn);
1871da177e4SLinus Torvalds break;
1881da177e4SLinus Torvalds }
1891da177e4SLinus Torvalds /* Must be a card-based bridge. */
1901be9baa0SBjorn Helgaas pin = pci_swizzle_interrupt_pin(dev, pin);
1911da177e4SLinus Torvalds
1921da177e4SLinus Torvalds /* Move up the chain of bridges. */
1931da177e4SLinus Torvalds dev = dev->bus->self;
1941da177e4SLinus Torvalds }
1951da177e4SLinus Torvalds *pinp = pin;
1961da177e4SLinus Torvalds return slot;
1971da177e4SLinus Torvalds }
1981da177e4SLinus Torvalds
1991da177e4SLinus Torvalds /*
2001da177e4SLinus Torvalds * The System Vectors
2011da177e4SLinus Torvalds */
2021da177e4SLinus Torvalds
2031da177e4SLinus Torvalds struct alpha_machine_vector eiger_mv __initmv = {
2041da177e4SLinus Torvalds .vector_name = "Eiger",
2051da177e4SLinus Torvalds DO_EV6_MMU,
2061da177e4SLinus Torvalds DO_DEFAULT_RTC,
2071da177e4SLinus Torvalds DO_TSUNAMI_IO,
2081da177e4SLinus Torvalds .machine_check = tsunami_machine_check,
2091da177e4SLinus Torvalds .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
2101da177e4SLinus Torvalds .min_io_address = DEFAULT_IO_BASE,
2111da177e4SLinus Torvalds .min_mem_address = DEFAULT_MEM_BASE,
2121da177e4SLinus Torvalds .pci_dac_offset = TSUNAMI_DAC_OFFSET,
2131da177e4SLinus Torvalds
2141da177e4SLinus Torvalds .nr_irqs = 128,
2151da177e4SLinus Torvalds .device_interrupt = eiger_device_interrupt,
2161da177e4SLinus Torvalds
2171da177e4SLinus Torvalds .init_arch = tsunami_init_arch,
2181da177e4SLinus Torvalds .init_irq = eiger_init_irq,
2191da177e4SLinus Torvalds .init_rtc = common_init_rtc,
2201da177e4SLinus Torvalds .init_pci = common_init_pci,
2211da177e4SLinus Torvalds .kill_arch = tsunami_kill_arch,
2221da177e4SLinus Torvalds .pci_map_irq = eiger_map_irq,
2231da177e4SLinus Torvalds .pci_swizzle = eiger_swizzle,
2241da177e4SLinus Torvalds };
2251da177e4SLinus Torvalds ALIAS_MV(eiger)
226