1 /* 2 * linux/arch/alpha/kernel/sys_alcor.c 3 * 4 * Copyright (C) 1995 David A Rusling 5 * Copyright (C) 1996 Jay A Estabrook 6 * Copyright (C) 1998, 1999 Richard Henderson 7 * 8 * Code supporting the ALCOR and XLT (XL-300/366/433). 9 */ 10 11 #include <linux/config.h> 12 #include <linux/kernel.h> 13 #include <linux/types.h> 14 #include <linux/mm.h> 15 #include <linux/sched.h> 16 #include <linux/pci.h> 17 #include <linux/init.h> 18 #include <linux/reboot.h> 19 #include <linux/bitops.h> 20 21 #include <asm/ptrace.h> 22 #include <asm/system.h> 23 #include <asm/io.h> 24 #include <asm/dma.h> 25 #include <asm/mmu_context.h> 26 #include <asm/irq.h> 27 #include <asm/pgtable.h> 28 #include <asm/core_cia.h> 29 #include <asm/tlbflush.h> 30 31 #include "proto.h" 32 #include "irq_impl.h" 33 #include "pci_impl.h" 34 #include "machvec_impl.h" 35 36 37 /* Note mask bit is true for ENABLED irqs. */ 38 static unsigned long cached_irq_mask; 39 40 static inline void 41 alcor_update_irq_hw(unsigned long mask) 42 { 43 *(vuip)GRU_INT_MASK = mask; 44 mb(); 45 } 46 47 static inline void 48 alcor_enable_irq(unsigned int irq) 49 { 50 alcor_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16)); 51 } 52 53 static void 54 alcor_disable_irq(unsigned int irq) 55 { 56 alcor_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16))); 57 } 58 59 static void 60 alcor_mask_and_ack_irq(unsigned int irq) 61 { 62 alcor_disable_irq(irq); 63 64 /* On ALCOR/XLT, need to dismiss interrupt via GRU. */ 65 *(vuip)GRU_INT_CLEAR = 1 << (irq - 16); mb(); 66 *(vuip)GRU_INT_CLEAR = 0; mb(); 67 } 68 69 static unsigned int 70 alcor_startup_irq(unsigned int irq) 71 { 72 alcor_enable_irq(irq); 73 return 0; 74 } 75 76 static void 77 alcor_isa_mask_and_ack_irq(unsigned int irq) 78 { 79 i8259a_mask_and_ack_irq(irq); 80 81 /* On ALCOR/XLT, need to dismiss interrupt via GRU. */ 82 *(vuip)GRU_INT_CLEAR = 0x80000000; mb(); 83 *(vuip)GRU_INT_CLEAR = 0; mb(); 84 } 85 86 static void 87 alcor_end_irq(unsigned int irq) 88 { 89 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 90 alcor_enable_irq(irq); 91 } 92 93 static struct hw_interrupt_type alcor_irq_type = { 94 .typename = "ALCOR", 95 .startup = alcor_startup_irq, 96 .shutdown = alcor_disable_irq, 97 .enable = alcor_enable_irq, 98 .disable = alcor_disable_irq, 99 .ack = alcor_mask_and_ack_irq, 100 .end = alcor_end_irq, 101 }; 102 103 static void 104 alcor_device_interrupt(unsigned long vector, struct pt_regs *regs) 105 { 106 unsigned long pld; 107 unsigned int i; 108 109 /* Read the interrupt summary register of the GRU */ 110 pld = (*(vuip)GRU_INT_REQ) & GRU_INT_REQ_BITS; 111 112 /* 113 * Now for every possible bit set, work through them and call 114 * the appropriate interrupt handler. 115 */ 116 while (pld) { 117 i = ffz(~pld); 118 pld &= pld - 1; /* clear least bit set */ 119 if (i == 31) { 120 isa_device_interrupt(vector, regs); 121 } else { 122 handle_irq(16 + i, regs); 123 } 124 } 125 } 126 127 static void __init 128 alcor_init_irq(void) 129 { 130 long i; 131 132 if (alpha_using_srm) 133 alpha_mv.device_interrupt = srm_device_interrupt; 134 135 *(vuip)GRU_INT_MASK = 0; mb(); /* all disabled */ 136 *(vuip)GRU_INT_EDGE = 0; mb(); /* all are level */ 137 *(vuip)GRU_INT_HILO = 0x80000000U; mb(); /* ISA only HI */ 138 *(vuip)GRU_INT_CLEAR = 0; mb(); /* all clear */ 139 140 for (i = 16; i < 48; ++i) { 141 /* On Alcor, at least, lines 20..30 are not connected 142 and can generate spurrious interrupts if we turn them 143 on while IRQ probing. */ 144 if (i >= 16+20 && i <= 16+30) 145 continue; 146 irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; 147 irq_desc[i].handler = &alcor_irq_type; 148 } 149 i8259a_irq_type.ack = alcor_isa_mask_and_ack_irq; 150 151 init_i8259a_irqs(); 152 common_init_isa_dma(); 153 154 setup_irq(16+31, &isa_cascade_irqaction); 155 } 156 157 158 /* 159 * PCI Fixup configuration. 160 * 161 * Summary @ GRU_INT_REQ: 162 * Bit Meaning 163 * 0 Interrupt Line A from slot 2 164 * 1 Interrupt Line B from slot 2 165 * 2 Interrupt Line C from slot 2 166 * 3 Interrupt Line D from slot 2 167 * 4 Interrupt Line A from slot 1 168 * 5 Interrupt line B from slot 1 169 * 6 Interrupt Line C from slot 1 170 * 7 Interrupt Line D from slot 1 171 * 8 Interrupt Line A from slot 0 172 * 9 Interrupt Line B from slot 0 173 *10 Interrupt Line C from slot 0 174 *11 Interrupt Line D from slot 0 175 *12 Interrupt Line A from slot 4 176 *13 Interrupt Line B from slot 4 177 *14 Interrupt Line C from slot 4 178 *15 Interrupt Line D from slot 4 179 *16 Interrupt Line D from slot 3 180 *17 Interrupt Line D from slot 3 181 *18 Interrupt Line D from slot 3 182 *19 Interrupt Line D from slot 3 183 *20-30 Reserved 184 *31 EISA interrupt 185 * 186 * The device to slot mapping looks like: 187 * 188 * Slot Device 189 * 6 built-in TULIP (XLT only) 190 * 7 PCI on board slot 0 191 * 8 PCI on board slot 3 192 * 9 PCI on board slot 4 193 * 10 PCEB (PCI-EISA bridge) 194 * 11 PCI on board slot 2 195 * 12 PCI on board slot 1 196 * 197 * 198 * This two layered interrupt approach means that we allocate IRQ 16 and 199 * above for PCI interrupts. The IRQ relates to which bit the interrupt 200 * comes in on. This makes interrupt processing much easier. 201 */ 202 203 static int __init 204 alcor_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 205 { 206 static char irq_tab[7][5] __initdata = { 207 /*INT INTA INTB INTC INTD */ 208 /* note: IDSEL 17 is XLT only */ 209 {16+13, 16+13, 16+13, 16+13, 16+13}, /* IdSel 17, TULIP */ 210 { 16+8, 16+8, 16+9, 16+10, 16+11}, /* IdSel 18, slot 0 */ 211 {16+16, 16+16, 16+17, 16+18, 16+19}, /* IdSel 19, slot 3 */ 212 {16+12, 16+12, 16+13, 16+14, 16+15}, /* IdSel 20, slot 4 */ 213 { -1, -1, -1, -1, -1}, /* IdSel 21, PCEB */ 214 { 16+0, 16+0, 16+1, 16+2, 16+3}, /* IdSel 22, slot 2 */ 215 { 16+4, 16+4, 16+5, 16+6, 16+7}, /* IdSel 23, slot 1 */ 216 }; 217 const long min_idsel = 6, max_idsel = 12, irqs_per_slot = 5; 218 return COMMON_TABLE_LOOKUP; 219 } 220 221 static void 222 alcor_kill_arch(int mode) 223 { 224 cia_kill_arch(mode); 225 226 #ifndef ALPHA_RESTORE_SRM_SETUP 227 switch(mode) { 228 case LINUX_REBOOT_CMD_RESTART: 229 /* Who said DEC engineer's have no sense of humor? ;-) */ 230 if (alpha_using_srm) { 231 *(vuip) GRU_RESET = 0x0000dead; 232 mb(); 233 } 234 break; 235 case LINUX_REBOOT_CMD_HALT: 236 break; 237 case LINUX_REBOOT_CMD_POWER_OFF: 238 break; 239 } 240 241 halt(); 242 #endif 243 } 244 245 static void __init 246 alcor_init_pci(void) 247 { 248 struct pci_dev *dev; 249 250 cia_init_pci(); 251 252 /* 253 * Now we can look to see if we are really running on an XLT-type 254 * motherboard, by looking for a 21040 TULIP in slot 6, which is 255 * built into XLT and BRET/MAVERICK, but not available on ALCOR. 256 */ 257 dev = pci_get_device(PCI_VENDOR_ID_DEC, 258 PCI_DEVICE_ID_DEC_TULIP, 259 NULL); 260 if (dev && dev->devfn == PCI_DEVFN(6,0)) { 261 alpha_mv.sys.cia.gru_int_req_bits = XLT_GRU_INT_REQ_BITS; 262 printk(KERN_INFO "%s: Detected AS500 or XLT motherboard.\n", 263 __FUNCTION__); 264 } 265 pci_dev_put(dev); 266 } 267 268 269 /* 270 * The System Vectors 271 */ 272 273 struct alpha_machine_vector alcor_mv __initmv = { 274 .vector_name = "Alcor", 275 DO_EV5_MMU, 276 DO_DEFAULT_RTC, 277 DO_CIA_IO, 278 .machine_check = cia_machine_check, 279 .max_isa_dma_address = ALPHA_ALCOR_MAX_ISA_DMA_ADDRESS, 280 .min_io_address = EISA_DEFAULT_IO_BASE, 281 .min_mem_address = CIA_DEFAULT_MEM_BASE, 282 283 .nr_irqs = 48, 284 .device_interrupt = alcor_device_interrupt, 285 286 .init_arch = cia_init_arch, 287 .init_irq = alcor_init_irq, 288 .init_rtc = common_init_rtc, 289 .init_pci = alcor_init_pci, 290 .kill_arch = alcor_kill_arch, 291 .pci_map_irq = alcor_map_irq, 292 .pci_swizzle = common_swizzle, 293 294 .sys = { .cia = { 295 .gru_int_req_bits = ALCOR_GRU_INT_REQ_BITS 296 }} 297 }; 298 ALIAS_MV(alcor) 299 300 struct alpha_machine_vector xlt_mv __initmv = { 301 .vector_name = "XLT", 302 DO_EV5_MMU, 303 DO_DEFAULT_RTC, 304 DO_CIA_IO, 305 .machine_check = cia_machine_check, 306 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 307 .min_io_address = EISA_DEFAULT_IO_BASE, 308 .min_mem_address = CIA_DEFAULT_MEM_BASE, 309 310 .nr_irqs = 48, 311 .device_interrupt = alcor_device_interrupt, 312 313 .init_arch = cia_init_arch, 314 .init_irq = alcor_init_irq, 315 .init_rtc = common_init_rtc, 316 .init_pci = alcor_init_pci, 317 .kill_arch = alcor_kill_arch, 318 .pci_map_irq = alcor_map_irq, 319 .pci_swizzle = common_swizzle, 320 321 .sys = { .cia = { 322 .gru_int_req_bits = XLT_GRU_INT_REQ_BITS 323 }} 324 }; 325 326 /* No alpha_mv alias for XLT, since we compile it in unconditionally 327 with ALCOR; setup_arch knows how to cope. */ 328