1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * linux/arch/alpha/kernel/pci_impl.h 4 * 5 * This file contains declarations and inline functions for interfacing 6 * with the PCI initialization routines. 7 */ 8 9 struct pci_dev; 10 struct pci_controller; 11 struct pci_iommu_arena; 12 13 /* 14 * We can't just blindly use 64K for machines with EISA busses; they 15 * may also have PCI-PCI bridges present, and then we'd configure the 16 * bridge incorrectly. 17 * 18 * Also, we start at 0x8000 or 0x9000, in hopes to get all devices' 19 * IO space areas allocated *before* 0xC000; this is because certain 20 * BIOSes (Millennium for one) use PCI Config space "mechanism #2" 21 * accesses to probe the bus. If a device's registers appear at 0xC000, 22 * it may see an INx/OUTx at that address during BIOS emulation of the 23 * VGA BIOS, and some cards, notably Adaptec 2940UW, take mortal offense. 24 */ 25 26 #define EISA_DEFAULT_IO_BASE 0x9000 /* start above 8th slot */ 27 #define DEFAULT_IO_BASE 0x8000 /* start at 8th slot */ 28 29 /* 30 * We try to make the DEFAULT_MEM_BASE addresses *always* have more than 31 * a single bit set. This is so that devices like the broken Myrinet card 32 * will always have a PCI memory address that will never match a IDSEL 33 * address in PCI Config space, which can cause problems with early rev cards. 34 */ 35 36 /* 37 * An XL is AVANTI (APECS) family, *but* it has only 27 bits of ISA address 38 * that get passed through the PCI<->ISA bridge chip. Although this causes 39 * us to set the PCI->Mem window bases lower than normal, we still allocate 40 * PCI bus devices' memory addresses *below* the low DMA mapping window, 41 * and hope they fit below 64Mb (to avoid conflicts), and so that they can 42 * be accessed via SPARSE space. 43 * 44 * We accept the risk that a broken Myrinet card will be put into a true XL 45 * and thus can more easily run into the problem described below. 46 */ 47 #define XL_DEFAULT_MEM_BASE ((16+2)*1024*1024) /* 16M to 64M-1 is avail */ 48 49 /* 50 * APECS and LCA have only 34 bits for physical addresses, thus limiting PCI 51 * bus memory addresses for SPARSE access to be less than 128Mb. 52 */ 53 #define APECS_AND_LCA_DEFAULT_MEM_BASE ((16+2)*1024*1024) 54 55 /* 56 * Because MCPCIA and T2 core logic support more bits for 57 * physical addresses, they should allow an expanded range of SPARSE 58 * memory addresses. However, we do not use them all, in order to 59 * avoid the HAE manipulation that would be needed. 60 */ 61 #define MCPCIA_DEFAULT_MEM_BASE ((32+2)*1024*1024) 62 #define T2_DEFAULT_MEM_BASE ((16+1)*1024*1024) 63 64 /* 65 * Because CIA and PYXIS have more bits for physical addresses, 66 * they support an expanded range of SPARSE memory addresses. 67 */ 68 #define DEFAULT_MEM_BASE ((128+16)*1024*1024) 69 70 /* ??? Experimenting with no HAE for CIA. */ 71 #define CIA_DEFAULT_MEM_BASE ((32+2)*1024*1024) 72 73 #define IRONGATE_DEFAULT_MEM_BASE ((256*8-16)*1024*1024) 74 75 #define DEFAULT_AGP_APER_SIZE (64*1024*1024) 76 77 /* 78 * A small note about bridges and interrupts. The DECchip 21050 (and 79 * later) adheres to the PCI-PCI bridge specification. This says that 80 * the interrupts on the other side of a bridge are swizzled in the 81 * following manner: 82 * 83 * Dev Interrupt Interrupt 84 * Pin on Pin on 85 * Device Connector 86 * 87 * 4 A A 88 * B B 89 * C C 90 * D D 91 * 92 * 5 A B 93 * B C 94 * C D 95 * D A 96 * 97 * 6 A C 98 * B D 99 * C A 100 * D B 101 * 102 * 7 A D 103 * B A 104 * C B 105 * D C 106 * 107 * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A. 108 * Thus, each swizzle is ((pin-1) + (device#-4)) % 4 109 * 110 * pci_swizzle_interrupt_pin() swizzles for exactly one bridge. The routine 111 * pci_common_swizzle() handles multiple bridges. But there are a 112 * couple boards that do strange things. 113 */ 114 115 116 /* The following macro is used to implement the table-based irq mapping 117 function for all single-bus Alphas. */ 118 119 #define COMMON_TABLE_LOOKUP \ 120 ({ long _ctl_ = -1; \ 121 if (slot >= min_idsel && slot <= max_idsel && pin < irqs_per_slot) \ 122 _ctl_ = irq_tab[slot - min_idsel][pin]; \ 123 _ctl_; }) 124 125 126 /* A PCI IOMMU allocation arena. There are typically two of these 127 regions per bus. */ 128 /* ??? The 8400 has a 32-byte pte entry, and the entire table apparently 129 lives directly on the host bridge (no tlb?). We don't support this 130 machine, but if we ever did, we'd need to parameterize all this quite 131 a bit further. Probably with per-bus operation tables. */ 132 133 struct pci_iommu_arena 134 { 135 spinlock_t lock; 136 struct pci_controller *hose; 137 #define IOMMU_INVALID_PTE 0x2 /* 32:63 bits MBZ */ 138 #define IOMMU_RESERVED_PTE 0xface 139 unsigned long *ptes; 140 dma_addr_t dma_base; 141 unsigned int size; 142 unsigned int next_entry; 143 unsigned int align_entry; 144 }; 145 146 #if defined(CONFIG_ALPHA_SRM) && \ 147 (defined(CONFIG_ALPHA_CIA) || defined(CONFIG_ALPHA_LCA) || \ 148 defined(CONFIG_ALPHA_AVANTI)) 149 # define NEED_SRM_SAVE_RESTORE 150 #else 151 # undef NEED_SRM_SAVE_RESTORE 152 #endif 153 154 #if defined(CONFIG_ALPHA_GENERIC) || defined(NEED_SRM_SAVE_RESTORE) 155 # define ALPHA_RESTORE_SRM_SETUP 156 #else 157 # undef ALPHA_RESTORE_SRM_SETUP 158 #endif 159 160 #ifdef ALPHA_RESTORE_SRM_SETUP 161 extern void pci_restore_srm_config(void); 162 #else 163 #define pci_restore_srm_config() do {} while (0) 164 #endif 165 166 /* The hose list. */ 167 extern struct pci_controller *hose_head, **hose_tail; 168 extern struct pci_controller *pci_isa_hose; 169 170 extern unsigned long alpha_agpgart_size; 171 172 extern void common_init_pci(void); 173 #define common_swizzle pci_common_swizzle 174 extern struct pci_controller *alloc_pci_controller(void); 175 extern struct resource *alloc_resource(void); 176 177 extern struct pci_iommu_arena *iommu_arena_new_node(int, 178 struct pci_controller *, 179 dma_addr_t, unsigned long, 180 unsigned long); 181 extern struct pci_iommu_arena *iommu_arena_new(struct pci_controller *, 182 dma_addr_t, unsigned long, 183 unsigned long); 184 extern const char *const pci_io_names[]; 185 extern const char *const pci_mem_names[]; 186 extern const char pci_hae0_name[]; 187 188 extern unsigned long size_for_memory(unsigned long max); 189 190 extern int iommu_reserve(struct pci_iommu_arena *, long, long); 191 extern int iommu_release(struct pci_iommu_arena *, long, long); 192 extern int iommu_bind(struct pci_iommu_arena *, long, long, struct page **); 193 extern int iommu_unbind(struct pci_iommu_arena *, long, long); 194 195 196