xref: /openbmc/linux/arch/alpha/kernel/pci.c (revision bc05aa6e) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  *	linux/arch/alpha/kernel/pci.c
4  *
5  * Extruded from code written by
6  *	Dave Rusling (david.rusling@reo.mts.dec.com)
7  *	David Mosberger (davidm@cs.arizona.edu)
8  */
9 
10 /* 2.3.x PCI/resources, 1999 Andrea Arcangeli <andrea@suse.de> */
11 
12 /*
13  * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14  *	     PCI-PCI bridges cleanup
15  */
16 #include <linux/string.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/ioport.h>
20 #include <linux/kernel.h>
21 #include <linux/bootmem.h>
22 #include <linux/module.h>
23 #include <linux/cache.h>
24 #include <linux/slab.h>
25 #include <asm/machvec.h>
26 
27 #include "proto.h"
28 #include "pci_impl.h"
29 
30 
31 /*
32  * Some string constants used by the various core logics.
33  */
34 
35 const char *const pci_io_names[] = {
36   "PCI IO bus 0", "PCI IO bus 1", "PCI IO bus 2", "PCI IO bus 3",
37   "PCI IO bus 4", "PCI IO bus 5", "PCI IO bus 6", "PCI IO bus 7"
38 };
39 
40 const char *const pci_mem_names[] = {
41   "PCI mem bus 0", "PCI mem bus 1", "PCI mem bus 2", "PCI mem bus 3",
42   "PCI mem bus 4", "PCI mem bus 5", "PCI mem bus 6", "PCI mem bus 7"
43 };
44 
45 const char pci_hae0_name[] = "HAE0";
46 
47 /*
48  * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
49  * assignments.
50  */
51 
52 /*
53  * The PCI controller list.
54  */
55 
56 struct pci_controller *hose_head, **hose_tail = &hose_head;
57 struct pci_controller *pci_isa_hose;
58 
59 /*
60  * Quirks.
61  */
62 
63 static void quirk_isa_bridge(struct pci_dev *dev)
64 {
65 	dev->class = PCI_CLASS_BRIDGE_ISA << 8;
66 }
67 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378, quirk_isa_bridge);
68 
69 static void quirk_cypress(struct pci_dev *dev)
70 {
71 	/* The Notorious Cy82C693 chip.  */
72 
73 	/* The generic legacy mode IDE fixup in drivers/pci/probe.c
74 	   doesn't work correctly with the Cypress IDE controller as
75 	   it has non-standard register layout.  Fix that.  */
76 	if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE) {
77 		dev->resource[2].start = dev->resource[3].start = 0;
78 		dev->resource[2].end = dev->resource[3].end = 0;
79 		dev->resource[2].flags = dev->resource[3].flags = 0;
80 		if (PCI_FUNC(dev->devfn) == 2) {
81 			dev->resource[0].start = 0x170;
82 			dev->resource[0].end = 0x177;
83 			dev->resource[1].start = 0x376;
84 			dev->resource[1].end = 0x376;
85 		}
86 	}
87 
88 	/* The Cypress bridge responds on the PCI bus in the address range
89 	   0xffff0000-0xffffffff (conventional x86 BIOS ROM).  There is no
90 	   way to turn this off.  The bridge also supports several extended
91 	   BIOS ranges (disabled after power-up), and some consoles do turn
92 	   them on.  So if we use a large direct-map window, or a large SG
93 	   window, we must avoid the entire 0xfff00000-0xffffffff region.  */
94 	if (dev->class >> 8 == PCI_CLASS_BRIDGE_ISA) {
95 		if (__direct_map_base + __direct_map_size >= 0xfff00000UL)
96 			__direct_map_size = 0xfff00000UL - __direct_map_base;
97 		else {
98 			struct pci_controller *hose = dev->sysdata;
99 			struct pci_iommu_arena *pci = hose->sg_pci;
100 			if (pci && pci->dma_base + pci->size >= 0xfff00000UL)
101 				pci->size = 0xfff00000UL - pci->dma_base;
102 		}
103 	}
104 }
105 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, quirk_cypress);
106 
107 /* Called for each device after PCI setup is done. */
108 static void pcibios_fixup_final(struct pci_dev *dev)
109 {
110 	unsigned int class = dev->class >> 8;
111 
112 	if (class == PCI_CLASS_BRIDGE_ISA || class == PCI_CLASS_BRIDGE_EISA) {
113 		dev->dma_mask = MAX_ISA_DMA_ADDRESS - 1;
114 		isa_bridge = dev;
115 	}
116 }
117 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);
118 
119 /* Just declaring that the power-of-ten prefixes are actually the
120    power-of-two ones doesn't make it true :) */
121 #define KB			1024
122 #define MB			(1024*KB)
123 #define GB			(1024*MB)
124 
125 resource_size_t
126 pcibios_align_resource(void *data, const struct resource *res,
127 		       resource_size_t size, resource_size_t align)
128 {
129 	struct pci_dev *dev = data;
130 	struct pci_controller *hose = dev->sysdata;
131 	unsigned long alignto;
132 	resource_size_t start = res->start;
133 
134 	if (res->flags & IORESOURCE_IO) {
135 		/* Make sure we start at our min on all hoses */
136 		if (start - hose->io_space->start < PCIBIOS_MIN_IO)
137 			start = PCIBIOS_MIN_IO + hose->io_space->start;
138 
139 		/*
140 		 * Put everything into 0x00-0xff region modulo 0x400
141 		 */
142 		if (start & 0x300)
143 			start = (start + 0x3ff) & ~0x3ff;
144 	}
145 	else if	(res->flags & IORESOURCE_MEM) {
146 		/* Make sure we start at our min on all hoses */
147 		if (start - hose->mem_space->start < PCIBIOS_MIN_MEM)
148 			start = PCIBIOS_MIN_MEM + hose->mem_space->start;
149 
150 		/*
151 		 * The following holds at least for the Low Cost
152 		 * Alpha implementation of the PCI interface:
153 		 *
154 		 * In sparse memory address space, the first
155 		 * octant (16MB) of every 128MB segment is
156 		 * aliased to the very first 16 MB of the
157 		 * address space (i.e., it aliases the ISA
158 		 * memory address space).  Thus, we try to
159 		 * avoid allocating PCI devices in that range.
160 		 * Can be allocated in 2nd-7th octant only.
161 		 * Devices that need more than 112MB of
162 		 * address space must be accessed through
163 		 * dense memory space only!
164 		 */
165 
166 		/* Align to multiple of size of minimum base.  */
167 		alignto = max_t(resource_size_t, 0x1000, align);
168 		start = ALIGN(start, alignto);
169 		if (hose->sparse_mem_base && size <= 7 * 16*MB) {
170 			if (((start / (16*MB)) & 0x7) == 0) {
171 				start &= ~(128*MB - 1);
172 				start += 16*MB;
173 				start  = ALIGN(start, alignto);
174 			}
175 			if (start/(128*MB) != (start + size - 1)/(128*MB)) {
176 				start &= ~(128*MB - 1);
177 				start += (128 + 16)*MB;
178 				start  = ALIGN(start, alignto);
179 			}
180 		}
181 	}
182 
183 	return start;
184 }
185 #undef KB
186 #undef MB
187 #undef GB
188 
189 static int __init
190 pcibios_init(void)
191 {
192 	if (alpha_mv.init_pci)
193 		alpha_mv.init_pci();
194 	return 0;
195 }
196 
197 subsys_initcall(pcibios_init);
198 
199 #ifdef ALPHA_RESTORE_SRM_SETUP
200 /* Store PCI device configuration left by SRM here. */
201 struct pdev_srm_saved_conf
202 {
203 	struct pdev_srm_saved_conf *next;
204 	struct pci_dev *dev;
205 };
206 
207 static struct pdev_srm_saved_conf *srm_saved_configs;
208 
209 static void pdev_save_srm_config(struct pci_dev *dev)
210 {
211 	struct pdev_srm_saved_conf *tmp;
212 	static int printed = 0;
213 
214 	if (!alpha_using_srm || pci_has_flag(PCI_PROBE_ONLY))
215 		return;
216 
217 	if (!printed) {
218 		printk(KERN_INFO "pci: enabling save/restore of SRM state\n");
219 		printed = 1;
220 	}
221 
222 	tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
223 	if (!tmp) {
224 		printk(KERN_ERR "%s: kmalloc() failed!\n", __func__);
225 		return;
226 	}
227 	tmp->next = srm_saved_configs;
228 	tmp->dev = dev;
229 
230 	pci_save_state(dev);
231 
232 	srm_saved_configs = tmp;
233 }
234 
235 void
236 pci_restore_srm_config(void)
237 {
238 	struct pdev_srm_saved_conf *tmp;
239 
240 	/* No need to restore if probed only. */
241 	if (pci_has_flag(PCI_PROBE_ONLY))
242 		return;
243 
244 	/* Restore SRM config. */
245 	for (tmp = srm_saved_configs; tmp; tmp = tmp->next) {
246 		pci_restore_state(tmp->dev);
247 	}
248 }
249 #else
250 #define pdev_save_srm_config(dev)	do {} while (0)
251 #endif
252 
253 void pcibios_fixup_bus(struct pci_bus *bus)
254 {
255 	struct pci_dev *dev = bus->self;
256 
257 	if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
258 	    (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
259 		pci_read_bridge_bases(bus);
260 	}
261 
262 	list_for_each_entry(dev, &bus->devices, bus_list) {
263 		pdev_save_srm_config(dev);
264 	}
265 }
266 
267 /*
268  *  If we set up a device for bus mastering, we need to check the latency
269  *  timer as certain firmware forgets to set it properly, as seen
270  *  on SX164 and LX164 with SRM.
271  */
272 void
273 pcibios_set_master(struct pci_dev *dev)
274 {
275 	u8 lat;
276 	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
277 	if (lat >= 16) return;
278 	printk("PCI: Setting latency timer of device %s to 64\n",
279 							pci_name(dev));
280 	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
281 }
282 
283 void __init
284 pcibios_claim_one_bus(struct pci_bus *b)
285 {
286 	struct pci_dev *dev;
287 	struct pci_bus *child_bus;
288 
289 	list_for_each_entry(dev, &b->devices, bus_list) {
290 		int i;
291 
292 		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
293 			struct resource *r = &dev->resource[i];
294 
295 			if (r->parent || !r->start || !r->flags)
296 				continue;
297 			if (pci_has_flag(PCI_PROBE_ONLY) ||
298 			    (r->flags & IORESOURCE_PCI_FIXED)) {
299 				if (pci_claim_resource(dev, i) == 0)
300 					continue;
301 
302 				pci_claim_bridge_resource(dev, i);
303 			}
304 		}
305 	}
306 
307 	list_for_each_entry(child_bus, &b->children, node)
308 		pcibios_claim_one_bus(child_bus);
309 }
310 
311 static void __init
312 pcibios_claim_console_setup(void)
313 {
314 	struct pci_bus *b;
315 
316 	list_for_each_entry(b, &pci_root_buses, node)
317 		pcibios_claim_one_bus(b);
318 }
319 
320 void __init
321 common_init_pci(void)
322 {
323 	struct pci_controller *hose;
324 	struct list_head resources;
325 	struct pci_host_bridge *bridge;
326 	struct pci_bus *bus;
327 	int ret, next_busno;
328 	int need_domain_info = 0;
329 	u32 pci_mem_end;
330 	u32 sg_base;
331 	unsigned long end;
332 
333 	/* Scan all of the recorded PCI controllers.  */
334 	for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
335 		sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0;
336 
337 		/* Adjust hose mem_space limit to prevent PCI allocations
338 		   in the iommu windows. */
339 		pci_mem_end = min((u32)__direct_map_base, sg_base) - 1;
340 		end = hose->mem_space->start + pci_mem_end;
341 		if (hose->mem_space->end > end)
342 			hose->mem_space->end = end;
343 
344 		INIT_LIST_HEAD(&resources);
345 		pci_add_resource_offset(&resources, hose->io_space,
346 					hose->io_space->start);
347 		pci_add_resource_offset(&resources, hose->mem_space,
348 					hose->mem_space->start);
349 
350 		bridge = pci_alloc_host_bridge(0);
351 		if (!bridge)
352 			continue;
353 
354 		list_splice_init(&resources, &bridge->windows);
355 		bridge->dev.parent = NULL;
356 		bridge->sysdata = hose;
357 		bridge->busnr = next_busno;
358 		bridge->ops = alpha_mv.pci_ops;
359 		bridge->swizzle_irq = alpha_mv.pci_swizzle;
360 		bridge->map_irq = alpha_mv.pci_map_irq;
361 
362 		ret = pci_scan_root_bus_bridge(bridge);
363 		if (ret) {
364 			pci_free_host_bridge(bridge);
365 			continue;
366 		}
367 
368 		bus = hose->bus = bridge->bus;
369 		hose->need_domain_info = need_domain_info;
370 		next_busno = bus->busn_res.end + 1;
371 		/* Don't allow 8-bit bus number overflow inside the hose -
372 		   reserve some space for bridges. */
373 		if (next_busno > 224) {
374 			next_busno = 0;
375 			need_domain_info = 1;
376 		}
377 	}
378 
379 	pcibios_claim_console_setup();
380 
381 	pci_assign_unassigned_resources();
382 	for (hose = hose_head; hose; hose = hose->next) {
383 		bus = hose->bus;
384 		if (bus)
385 			pci_bus_add_devices(bus);
386 	}
387 }
388 
389 struct pci_controller * __init
390 alloc_pci_controller(void)
391 {
392 	struct pci_controller *hose;
393 
394 	hose = alloc_bootmem(sizeof(*hose));
395 
396 	*hose_tail = hose;
397 	hose_tail = &hose->next;
398 
399 	return hose;
400 }
401 
402 struct resource * __init
403 alloc_resource(void)
404 {
405 	return alloc_bootmem(sizeof(struct resource));
406 }
407 
408 
409 /* Provide information on locations of various I/O regions in physical
410    memory.  Do this on a per-card basis so that we choose the right hose.  */
411 
412 asmlinkage long
413 sys_pciconfig_iobase(long which, unsigned long bus, unsigned long dfn)
414 {
415 	struct pci_controller *hose;
416 	struct pci_dev *dev;
417 
418 	/* from hose or from bus.devfn */
419 	if (which & IOBASE_FROM_HOSE) {
420 		for(hose = hose_head; hose; hose = hose->next)
421 			if (hose->index == bus) break;
422 		if (!hose) return -ENODEV;
423 	} else {
424 		/* Special hook for ISA access.  */
425 		if (bus == 0 && dfn == 0) {
426 			hose = pci_isa_hose;
427 		} else {
428 			dev = pci_get_domain_bus_and_slot(0, bus, dfn);
429 			if (!dev)
430 				return -ENODEV;
431 			hose = dev->sysdata;
432 			pci_dev_put(dev);
433 		}
434 	}
435 
436 	switch (which & ~IOBASE_FROM_HOSE) {
437 	case IOBASE_HOSE:
438 		return hose->index;
439 	case IOBASE_SPARSE_MEM:
440 		return hose->sparse_mem_base;
441 	case IOBASE_DENSE_MEM:
442 		return hose->dense_mem_base;
443 	case IOBASE_SPARSE_IO:
444 		return hose->sparse_io_base;
445 	case IOBASE_DENSE_IO:
446 		return hose->dense_io_base;
447 	case IOBASE_ROOT_BUS:
448 		return hose->bus->number;
449 	}
450 
451 	return -EOPNOTSUPP;
452 }
453 
454 /* Destroy an __iomem token.  Not copied from lib/iomap.c.  */
455 
456 void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
457 {
458 	if (__is_mmio(addr))
459 		iounmap(addr);
460 }
461 
462 EXPORT_SYMBOL(pci_iounmap);
463 
464 /* FIXME: Some boxes have multiple ISA bridges! */
465 struct pci_dev *isa_bridge;
466 EXPORT_SYMBOL(isa_bridge);
467