1 /* 2 * linux/arch/alpha/kernel/pci.c 3 * 4 * Extruded from code written by 5 * Dave Rusling (david.rusling@reo.mts.dec.com) 6 * David Mosberger (davidm@cs.arizona.edu) 7 */ 8 9 /* 2.3.x PCI/resources, 1999 Andrea Arcangeli <andrea@suse.de> */ 10 11 /* 12 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 13 * PCI-PCI bridges cleanup 14 */ 15 #include <linux/string.h> 16 #include <linux/pci.h> 17 #include <linux/init.h> 18 #include <linux/ioport.h> 19 #include <linux/kernel.h> 20 #include <linux/bootmem.h> 21 #include <linux/module.h> 22 #include <linux/cache.h> 23 #include <linux/slab.h> 24 #include <asm/machvec.h> 25 26 #include "proto.h" 27 #include "pci_impl.h" 28 29 30 /* 31 * Some string constants used by the various core logics. 32 */ 33 34 const char *const pci_io_names[] = { 35 "PCI IO bus 0", "PCI IO bus 1", "PCI IO bus 2", "PCI IO bus 3", 36 "PCI IO bus 4", "PCI IO bus 5", "PCI IO bus 6", "PCI IO bus 7" 37 }; 38 39 const char *const pci_mem_names[] = { 40 "PCI mem bus 0", "PCI mem bus 1", "PCI mem bus 2", "PCI mem bus 3", 41 "PCI mem bus 4", "PCI mem bus 5", "PCI mem bus 6", "PCI mem bus 7" 42 }; 43 44 const char pci_hae0_name[] = "HAE0"; 45 46 /* 47 * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource 48 * assignments. 49 */ 50 51 /* 52 * The PCI controller list. 53 */ 54 55 struct pci_controller *hose_head, **hose_tail = &hose_head; 56 struct pci_controller *pci_isa_hose; 57 58 /* 59 * Quirks. 60 */ 61 62 static void __devinit quirk_isa_bridge(struct pci_dev *dev) 63 { 64 dev->class = PCI_CLASS_BRIDGE_ISA << 8; 65 } 66 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378, quirk_isa_bridge); 67 68 static void __devinit quirk_cypress(struct pci_dev *dev) 69 { 70 /* The Notorious Cy82C693 chip. */ 71 72 /* The generic legacy mode IDE fixup in drivers/pci/probe.c 73 doesn't work correctly with the Cypress IDE controller as 74 it has non-standard register layout. Fix that. */ 75 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE) { 76 dev->resource[2].start = dev->resource[3].start = 0; 77 dev->resource[2].end = dev->resource[3].end = 0; 78 dev->resource[2].flags = dev->resource[3].flags = 0; 79 if (PCI_FUNC(dev->devfn) == 2) { 80 dev->resource[0].start = 0x170; 81 dev->resource[0].end = 0x177; 82 dev->resource[1].start = 0x376; 83 dev->resource[1].end = 0x376; 84 } 85 } 86 87 /* The Cypress bridge responds on the PCI bus in the address range 88 0xffff0000-0xffffffff (conventional x86 BIOS ROM). There is no 89 way to turn this off. The bridge also supports several extended 90 BIOS ranges (disabled after power-up), and some consoles do turn 91 them on. So if we use a large direct-map window, or a large SG 92 window, we must avoid the entire 0xfff00000-0xffffffff region. */ 93 if (dev->class >> 8 == PCI_CLASS_BRIDGE_ISA) { 94 if (__direct_map_base + __direct_map_size >= 0xfff00000UL) 95 __direct_map_size = 0xfff00000UL - __direct_map_base; 96 else { 97 struct pci_controller *hose = dev->sysdata; 98 struct pci_iommu_arena *pci = hose->sg_pci; 99 if (pci && pci->dma_base + pci->size >= 0xfff00000UL) 100 pci->size = 0xfff00000UL - pci->dma_base; 101 } 102 } 103 } 104 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, quirk_cypress); 105 106 /* Called for each device after PCI setup is done. */ 107 static void __devinit pcibios_fixup_final(struct pci_dev *dev) 108 { 109 unsigned int class = dev->class >> 8; 110 111 if (class == PCI_CLASS_BRIDGE_ISA || class == PCI_CLASS_BRIDGE_EISA) { 112 dev->dma_mask = MAX_ISA_DMA_ADDRESS - 1; 113 isa_bridge = dev; 114 } 115 } 116 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final); 117 118 /* Just declaring that the power-of-ten prefixes are actually the 119 power-of-two ones doesn't make it true :) */ 120 #define KB 1024 121 #define MB (1024*KB) 122 #define GB (1024*MB) 123 124 resource_size_t 125 pcibios_align_resource(void *data, const struct resource *res, 126 resource_size_t size, resource_size_t align) 127 { 128 struct pci_dev *dev = data; 129 struct pci_controller *hose = dev->sysdata; 130 unsigned long alignto; 131 resource_size_t start = res->start; 132 133 if (res->flags & IORESOURCE_IO) { 134 /* Make sure we start at our min on all hoses */ 135 if (start - hose->io_space->start < PCIBIOS_MIN_IO) 136 start = PCIBIOS_MIN_IO + hose->io_space->start; 137 138 /* 139 * Put everything into 0x00-0xff region modulo 0x400 140 */ 141 if (start & 0x300) 142 start = (start + 0x3ff) & ~0x3ff; 143 } 144 else if (res->flags & IORESOURCE_MEM) { 145 /* Make sure we start at our min on all hoses */ 146 if (start - hose->mem_space->start < PCIBIOS_MIN_MEM) 147 start = PCIBIOS_MIN_MEM + hose->mem_space->start; 148 149 /* 150 * The following holds at least for the Low Cost 151 * Alpha implementation of the PCI interface: 152 * 153 * In sparse memory address space, the first 154 * octant (16MB) of every 128MB segment is 155 * aliased to the very first 16 MB of the 156 * address space (i.e., it aliases the ISA 157 * memory address space). Thus, we try to 158 * avoid allocating PCI devices in that range. 159 * Can be allocated in 2nd-7th octant only. 160 * Devices that need more than 112MB of 161 * address space must be accessed through 162 * dense memory space only! 163 */ 164 165 /* Align to multiple of size of minimum base. */ 166 alignto = max_t(resource_size_t, 0x1000, align); 167 start = ALIGN(start, alignto); 168 if (hose->sparse_mem_base && size <= 7 * 16*MB) { 169 if (((start / (16*MB)) & 0x7) == 0) { 170 start &= ~(128*MB - 1); 171 start += 16*MB; 172 start = ALIGN(start, alignto); 173 } 174 if (start/(128*MB) != (start + size - 1)/(128*MB)) { 175 start &= ~(128*MB - 1); 176 start += (128 + 16)*MB; 177 start = ALIGN(start, alignto); 178 } 179 } 180 } 181 182 return start; 183 } 184 #undef KB 185 #undef MB 186 #undef GB 187 188 static int __init 189 pcibios_init(void) 190 { 191 if (alpha_mv.init_pci) 192 alpha_mv.init_pci(); 193 return 0; 194 } 195 196 subsys_initcall(pcibios_init); 197 198 #ifdef ALPHA_RESTORE_SRM_SETUP 199 static struct pdev_srm_saved_conf *srm_saved_configs; 200 201 void __devinit 202 pdev_save_srm_config(struct pci_dev *dev) 203 { 204 struct pdev_srm_saved_conf *tmp; 205 static int printed = 0; 206 207 if (!alpha_using_srm || pci_has_flag(PCI_PROBE_ONLY)) 208 return; 209 210 if (!printed) { 211 printk(KERN_INFO "pci: enabling save/restore of SRM state\n"); 212 printed = 1; 213 } 214 215 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); 216 if (!tmp) { 217 printk(KERN_ERR "%s: kmalloc() failed!\n", __func__); 218 return; 219 } 220 tmp->next = srm_saved_configs; 221 tmp->dev = dev; 222 223 pci_save_state(dev); 224 225 srm_saved_configs = tmp; 226 } 227 228 void 229 pci_restore_srm_config(void) 230 { 231 struct pdev_srm_saved_conf *tmp; 232 233 /* No need to restore if probed only. */ 234 if (pci_has_flag(PCI_PROBE_ONLY)) 235 return; 236 237 /* Restore SRM config. */ 238 for (tmp = srm_saved_configs; tmp; tmp = tmp->next) { 239 pci_restore_state(tmp->dev); 240 } 241 } 242 #endif 243 244 void __devinit 245 pcibios_fixup_bus(struct pci_bus *bus) 246 { 247 struct pci_dev *dev = bus->self; 248 249 if (pci_has_flag(PCI_PROBE_ONLY) && dev && 250 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 251 pci_read_bridge_bases(bus); 252 } 253 254 list_for_each_entry(dev, &bus->devices, bus_list) { 255 pdev_save_srm_config(dev); 256 } 257 } 258 259 void __init 260 pcibios_update_irq(struct pci_dev *dev, int irq) 261 { 262 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); 263 } 264 265 int 266 pcibios_enable_device(struct pci_dev *dev, int mask) 267 { 268 return pci_enable_resources(dev, mask); 269 } 270 271 /* 272 * If we set up a device for bus mastering, we need to check the latency 273 * timer as certain firmware forgets to set it properly, as seen 274 * on SX164 and LX164 with SRM. 275 */ 276 void 277 pcibios_set_master(struct pci_dev *dev) 278 { 279 u8 lat; 280 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 281 if (lat >= 16) return; 282 printk("PCI: Setting latency timer of device %s to 64\n", 283 pci_name(dev)); 284 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); 285 } 286 287 void __init 288 pcibios_claim_one_bus(struct pci_bus *b) 289 { 290 struct pci_dev *dev; 291 struct pci_bus *child_bus; 292 293 list_for_each_entry(dev, &b->devices, bus_list) { 294 int i; 295 296 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 297 struct resource *r = &dev->resource[i]; 298 299 if (r->parent || !r->start || !r->flags) 300 continue; 301 if (pci_has_flag(PCI_PROBE_ONLY) || 302 (r->flags & IORESOURCE_PCI_FIXED)) 303 pci_claim_resource(dev, i); 304 } 305 } 306 307 list_for_each_entry(child_bus, &b->children, node) 308 pcibios_claim_one_bus(child_bus); 309 } 310 311 static void __init 312 pcibios_claim_console_setup(void) 313 { 314 struct pci_bus *b; 315 316 list_for_each_entry(b, &pci_root_buses, node) 317 pcibios_claim_one_bus(b); 318 } 319 320 void __init 321 common_init_pci(void) 322 { 323 struct pci_controller *hose; 324 struct list_head resources; 325 struct pci_bus *bus; 326 int next_busno; 327 int need_domain_info = 0; 328 u32 pci_mem_end; 329 u32 sg_base; 330 unsigned long end; 331 332 /* Scan all of the recorded PCI controllers. */ 333 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) { 334 sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0; 335 336 /* Adjust hose mem_space limit to prevent PCI allocations 337 in the iommu windows. */ 338 pci_mem_end = min((u32)__direct_map_base, sg_base) - 1; 339 end = hose->mem_space->start + pci_mem_end; 340 if (hose->mem_space->end > end) 341 hose->mem_space->end = end; 342 343 INIT_LIST_HEAD(&resources); 344 pci_add_resource_offset(&resources, hose->io_space, 345 hose->io_space->start); 346 pci_add_resource_offset(&resources, hose->mem_space, 347 hose->mem_space->start); 348 349 bus = pci_scan_root_bus(NULL, next_busno, alpha_mv.pci_ops, 350 hose, &resources); 351 hose->bus = bus; 352 hose->need_domain_info = need_domain_info; 353 next_busno = bus->busn_res.end + 1; 354 /* Don't allow 8-bit bus number overflow inside the hose - 355 reserve some space for bridges. */ 356 if (next_busno > 224) { 357 next_busno = 0; 358 need_domain_info = 1; 359 } 360 } 361 362 pcibios_claim_console_setup(); 363 364 pci_assign_unassigned_resources(); 365 pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq); 366 } 367 368 369 struct pci_controller * __init 370 alloc_pci_controller(void) 371 { 372 struct pci_controller *hose; 373 374 hose = alloc_bootmem(sizeof(*hose)); 375 376 *hose_tail = hose; 377 hose_tail = &hose->next; 378 379 return hose; 380 } 381 382 struct resource * __init 383 alloc_resource(void) 384 { 385 struct resource *res; 386 387 res = alloc_bootmem(sizeof(*res)); 388 389 return res; 390 } 391 392 393 /* Provide information on locations of various I/O regions in physical 394 memory. Do this on a per-card basis so that we choose the right hose. */ 395 396 asmlinkage long 397 sys_pciconfig_iobase(long which, unsigned long bus, unsigned long dfn) 398 { 399 struct pci_controller *hose; 400 struct pci_dev *dev; 401 402 /* from hose or from bus.devfn */ 403 if (which & IOBASE_FROM_HOSE) { 404 for(hose = hose_head; hose; hose = hose->next) 405 if (hose->index == bus) break; 406 if (!hose) return -ENODEV; 407 } else { 408 /* Special hook for ISA access. */ 409 if (bus == 0 && dfn == 0) { 410 hose = pci_isa_hose; 411 } else { 412 dev = pci_get_bus_and_slot(bus, dfn); 413 if (!dev) 414 return -ENODEV; 415 hose = dev->sysdata; 416 pci_dev_put(dev); 417 } 418 } 419 420 switch (which & ~IOBASE_FROM_HOSE) { 421 case IOBASE_HOSE: 422 return hose->index; 423 case IOBASE_SPARSE_MEM: 424 return hose->sparse_mem_base; 425 case IOBASE_DENSE_MEM: 426 return hose->dense_mem_base; 427 case IOBASE_SPARSE_IO: 428 return hose->sparse_io_base; 429 case IOBASE_DENSE_IO: 430 return hose->dense_io_base; 431 case IOBASE_ROOT_BUS: 432 return hose->bus->number; 433 } 434 435 return -EOPNOTSUPP; 436 } 437 438 /* Destroy an __iomem token. Not copied from lib/iomap.c. */ 439 440 void pci_iounmap(struct pci_dev *dev, void __iomem * addr) 441 { 442 if (__is_mmio(addr)) 443 iounmap(addr); 444 } 445 446 EXPORT_SYMBOL(pci_iounmap); 447 448 /* FIXME: Some boxes have multiple ISA bridges! */ 449 struct pci_dev *isa_bridge; 450 EXPORT_SYMBOL(isa_bridge); 451