1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * linux/arch/alpha/kernel/irq_i8259.c 4 * 5 * This is the 'legacy' 8259A Programmable Interrupt Controller, 6 * present in the majority of PC/AT boxes. 7 * 8 * Started hacking from linux-2.3.30pre6/arch/i386/kernel/i8259.c. 9 */ 10 11 #include <linux/init.h> 12 #include <linux/cache.h> 13 #include <linux/sched.h> 14 #include <linux/irq.h> 15 #include <linux/interrupt.h> 16 17 #include <asm/io.h> 18 19 #include "proto.h" 20 #include "irq_impl.h" 21 22 23 /* Note mask bit is true for DISABLED irqs. */ 24 static unsigned int cached_irq_mask = 0xffff; 25 static DEFINE_SPINLOCK(i8259_irq_lock); 26 27 static inline void 28 i8259_update_irq_hw(unsigned int irq, unsigned long mask) 29 { 30 int port = 0x21; 31 if (irq & 8) mask >>= 8; 32 if (irq & 8) port = 0xA1; 33 outb(mask, port); 34 } 35 36 inline void 37 i8259a_enable_irq(struct irq_data *d) 38 { 39 spin_lock(&i8259_irq_lock); 40 i8259_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << d->irq)); 41 spin_unlock(&i8259_irq_lock); 42 } 43 44 static inline void 45 __i8259a_disable_irq(unsigned int irq) 46 { 47 i8259_update_irq_hw(irq, cached_irq_mask |= 1 << irq); 48 } 49 50 void 51 i8259a_disable_irq(struct irq_data *d) 52 { 53 spin_lock(&i8259_irq_lock); 54 __i8259a_disable_irq(d->irq); 55 spin_unlock(&i8259_irq_lock); 56 } 57 58 void 59 i8259a_mask_and_ack_irq(struct irq_data *d) 60 { 61 unsigned int irq = d->irq; 62 63 spin_lock(&i8259_irq_lock); 64 __i8259a_disable_irq(irq); 65 66 /* Ack the interrupt making it the lowest priority. */ 67 if (irq >= 8) { 68 outb(0xE0 | (irq - 8), 0xa0); /* ack the slave */ 69 irq = 2; 70 } 71 outb(0xE0 | irq, 0x20); /* ack the master */ 72 spin_unlock(&i8259_irq_lock); 73 } 74 75 struct irq_chip i8259a_irq_type = { 76 .name = "XT-PIC", 77 .irq_unmask = i8259a_enable_irq, 78 .irq_mask = i8259a_disable_irq, 79 .irq_mask_ack = i8259a_mask_and_ack_irq, 80 }; 81 82 void __init 83 init_i8259a_irqs(void) 84 { 85 static struct irqaction cascade = { 86 .handler = no_action, 87 .name = "cascade", 88 }; 89 90 long i; 91 92 outb(0xff, 0x21); /* mask all of 8259A-1 */ 93 outb(0xff, 0xA1); /* mask all of 8259A-2 */ 94 95 for (i = 0; i < 16; i++) { 96 irq_set_chip_and_handler(i, &i8259a_irq_type, handle_level_irq); 97 } 98 99 setup_irq(2, &cascade); 100 } 101 102 103 #if defined(CONFIG_ALPHA_GENERIC) 104 # define IACK_SC alpha_mv.iack_sc 105 #elif defined(CONFIG_ALPHA_APECS) 106 # define IACK_SC APECS_IACK_SC 107 #elif defined(CONFIG_ALPHA_LCA) 108 # define IACK_SC LCA_IACK_SC 109 #elif defined(CONFIG_ALPHA_CIA) 110 # define IACK_SC CIA_IACK_SC 111 #elif defined(CONFIG_ALPHA_PYXIS) 112 # define IACK_SC PYXIS_IACK_SC 113 #elif defined(CONFIG_ALPHA_TITAN) 114 # define IACK_SC TITAN_IACK_SC 115 #elif defined(CONFIG_ALPHA_TSUNAMI) 116 # define IACK_SC TSUNAMI_IACK_SC 117 #elif defined(CONFIG_ALPHA_IRONGATE) 118 # define IACK_SC IRONGATE_IACK_SC 119 #endif 120 /* Note that CONFIG_ALPHA_POLARIS is intentionally left out here, since 121 sys_rx164 wants to use isa_no_iack_sc_device_interrupt for some reason. */ 122 123 #if defined(IACK_SC) 124 void 125 isa_device_interrupt(unsigned long vector) 126 { 127 /* 128 * Generate a PCI interrupt acknowledge cycle. The PIC will 129 * respond with the interrupt vector of the highest priority 130 * interrupt that is pending. The PALcode sets up the 131 * interrupts vectors such that irq level L generates vector L. 132 */ 133 int j = *(vuip) IACK_SC; 134 j &= 0xff; 135 handle_irq(j); 136 } 137 #endif 138 139 #if defined(CONFIG_ALPHA_GENERIC) || !defined(IACK_SC) 140 void 141 isa_no_iack_sc_device_interrupt(unsigned long vector) 142 { 143 unsigned long pic; 144 145 /* 146 * It seems to me that the probability of two or more *device* 147 * interrupts occurring at almost exactly the same time is 148 * pretty low. So why pay the price of checking for 149 * additional interrupts here if the common case can be 150 * handled so much easier? 151 */ 152 /* 153 * The first read of gives you *all* interrupting lines. 154 * Therefore, read the mask register and and out those lines 155 * not enabled. Note that some documentation has 21 and a1 156 * write only. This is not true. 157 */ 158 pic = inb(0x20) | (inb(0xA0) << 8); /* read isr */ 159 pic &= 0xFFFB; /* mask out cascade & hibits */ 160 161 while (pic) { 162 int j = ffz(~pic); 163 pic &= pic - 1; 164 handle_irq(j); 165 } 166 } 167 #endif 168