1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * linux/arch/alpha/kernel/core_wildfire.c 4 * 5 * Wildfire support. 6 * 7 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE 8 */ 9 10 #define __EXTERN_INLINE inline 11 #include <asm/io.h> 12 #include <asm/core_wildfire.h> 13 #undef __EXTERN_INLINE 14 15 #include <linux/types.h> 16 #include <linux/pci.h> 17 #include <linux/sched.h> 18 #include <linux/init.h> 19 20 #include <asm/ptrace.h> 21 #include <asm/smp.h> 22 23 #include "proto.h" 24 #include "pci_impl.h" 25 26 #define DEBUG_CONFIG 0 27 #define DEBUG_DUMP_REGS 0 28 #define DEBUG_DUMP_CONFIG 1 29 30 #if DEBUG_CONFIG 31 # define DBG_CFG(args) printk args 32 #else 33 # define DBG_CFG(args) 34 #endif 35 36 #if DEBUG_DUMP_REGS 37 static void wildfire_dump_pci_regs(int qbbno, int hoseno); 38 static void wildfire_dump_pca_regs(int qbbno, int pcano); 39 static void wildfire_dump_qsa_regs(int qbbno); 40 static void wildfire_dump_qsd_regs(int qbbno); 41 static void wildfire_dump_iop_regs(int qbbno); 42 static void wildfire_dump_gp_regs(int qbbno); 43 #endif 44 #if DEBUG_DUMP_CONFIG 45 static void wildfire_dump_hardware_config(void); 46 #endif 47 48 unsigned char wildfire_hard_qbb_map[WILDFIRE_MAX_QBB]; 49 unsigned char wildfire_soft_qbb_map[WILDFIRE_MAX_QBB]; 50 #define QBB_MAP_EMPTY 0xff 51 52 unsigned long wildfire_hard_qbb_mask; 53 unsigned long wildfire_soft_qbb_mask; 54 unsigned long wildfire_gp_mask; 55 unsigned long wildfire_hs_mask; 56 unsigned long wildfire_iop_mask; 57 unsigned long wildfire_ior_mask; 58 unsigned long wildfire_pca_mask; 59 unsigned long wildfire_cpu_mask; 60 unsigned long wildfire_mem_mask; 61 62 void __init 63 wildfire_init_hose(int qbbno, int hoseno) 64 { 65 struct pci_controller *hose; 66 wildfire_pci *pci; 67 68 hose = alloc_pci_controller(); 69 hose->io_space = alloc_resource(); 70 hose->mem_space = alloc_resource(); 71 72 /* This is for userland consumption. */ 73 hose->sparse_mem_base = 0; 74 hose->sparse_io_base = 0; 75 hose->dense_mem_base = WILDFIRE_MEM(qbbno, hoseno); 76 hose->dense_io_base = WILDFIRE_IO(qbbno, hoseno); 77 78 hose->config_space_base = WILDFIRE_CONF(qbbno, hoseno); 79 hose->index = (qbbno << 3) + hoseno; 80 81 hose->io_space->start = WILDFIRE_IO(qbbno, hoseno) - WILDFIRE_IO_BIAS; 82 hose->io_space->end = hose->io_space->start + WILDFIRE_IO_SPACE - 1; 83 hose->io_space->name = pci_io_names[hoseno]; 84 hose->io_space->flags = IORESOURCE_IO; 85 86 hose->mem_space->start = WILDFIRE_MEM(qbbno, hoseno)-WILDFIRE_MEM_BIAS; 87 hose->mem_space->end = hose->mem_space->start + 0xffffffff; 88 hose->mem_space->name = pci_mem_names[hoseno]; 89 hose->mem_space->flags = IORESOURCE_MEM; 90 91 if (request_resource(&ioport_resource, hose->io_space) < 0) 92 printk(KERN_ERR "Failed to request IO on qbb %d hose %d\n", 93 qbbno, hoseno); 94 if (request_resource(&iomem_resource, hose->mem_space) < 0) 95 printk(KERN_ERR "Failed to request MEM on qbb %d hose %d\n", 96 qbbno, hoseno); 97 98 #if DEBUG_DUMP_REGS 99 wildfire_dump_pci_regs(qbbno, hoseno); 100 #endif 101 102 /* 103 * Set up the PCI to main memory translation windows. 104 * 105 * Note: Window 3 is scatter-gather only 106 * 107 * Window 0 is scatter-gather 8MB at 8MB (for isa) 108 * Window 1 is direct access 1GB at 1GB 109 * Window 2 is direct access 1GB at 2GB 110 * Window 3 is scatter-gather 128MB at 3GB 111 * ??? We ought to scale window 3 memory. 112 * 113 */ 114 hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, 0); 115 hose->sg_pci = iommu_arena_new(hose, 0xc0000000, 0x08000000, 0); 116 117 pci = WILDFIRE_pci(qbbno, hoseno); 118 119 pci->pci_window[0].wbase.csr = hose->sg_isa->dma_base | 3; 120 pci->pci_window[0].wmask.csr = (hose->sg_isa->size - 1) & 0xfff00000; 121 pci->pci_window[0].tbase.csr = virt_to_phys(hose->sg_isa->ptes); 122 123 pci->pci_window[1].wbase.csr = 0x40000000 | 1; 124 pci->pci_window[1].wmask.csr = (0x40000000 -1) & 0xfff00000; 125 pci->pci_window[1].tbase.csr = 0; 126 127 pci->pci_window[2].wbase.csr = 0x80000000 | 1; 128 pci->pci_window[2].wmask.csr = (0x40000000 -1) & 0xfff00000; 129 pci->pci_window[2].tbase.csr = 0x40000000; 130 131 pci->pci_window[3].wbase.csr = hose->sg_pci->dma_base | 3; 132 pci->pci_window[3].wmask.csr = (hose->sg_pci->size - 1) & 0xfff00000; 133 pci->pci_window[3].tbase.csr = virt_to_phys(hose->sg_pci->ptes); 134 135 wildfire_pci_tbi(hose, 0, 0); /* Flush TLB at the end. */ 136 } 137 138 void __init 139 wildfire_init_pca(int qbbno, int pcano) 140 { 141 142 /* Test for PCA existence first. */ 143 if (!WILDFIRE_PCA_EXISTS(qbbno, pcano)) 144 return; 145 146 #if DEBUG_DUMP_REGS 147 wildfire_dump_pca_regs(qbbno, pcano); 148 #endif 149 150 /* Do both hoses of the PCA. */ 151 wildfire_init_hose(qbbno, (pcano << 1) + 0); 152 wildfire_init_hose(qbbno, (pcano << 1) + 1); 153 } 154 155 void __init 156 wildfire_init_qbb(int qbbno) 157 { 158 int pcano; 159 160 /* Test for QBB existence first. */ 161 if (!WILDFIRE_QBB_EXISTS(qbbno)) 162 return; 163 164 #if DEBUG_DUMP_REGS 165 wildfire_dump_qsa_regs(qbbno); 166 wildfire_dump_qsd_regs(qbbno); 167 wildfire_dump_iop_regs(qbbno); 168 wildfire_dump_gp_regs(qbbno); 169 #endif 170 171 /* Init all PCAs here. */ 172 for (pcano = 0; pcano < WILDFIRE_PCA_PER_QBB; pcano++) { 173 wildfire_init_pca(qbbno, pcano); 174 } 175 } 176 177 void __init 178 wildfire_hardware_probe(void) 179 { 180 unsigned long temp; 181 unsigned int hard_qbb, soft_qbb; 182 wildfire_fast_qsd *fast = WILDFIRE_fast_qsd(); 183 wildfire_qsd *qsd; 184 wildfire_qsa *qsa; 185 wildfire_iop *iop; 186 wildfire_gp *gp; 187 wildfire_ne *ne; 188 wildfire_fe *fe; 189 int i; 190 191 temp = fast->qsd_whami.csr; 192 #if 0 193 printk(KERN_ERR "fast QSD_WHAMI at base %p is 0x%lx\n", fast, temp); 194 #endif 195 196 hard_qbb = (temp >> 8) & 7; 197 soft_qbb = (temp >> 4) & 7; 198 199 /* Init the HW configuration variables. */ 200 wildfire_hard_qbb_mask = (1 << hard_qbb); 201 wildfire_soft_qbb_mask = (1 << soft_qbb); 202 203 wildfire_gp_mask = 0; 204 wildfire_hs_mask = 0; 205 wildfire_iop_mask = 0; 206 wildfire_ior_mask = 0; 207 wildfire_pca_mask = 0; 208 209 wildfire_cpu_mask = 0; 210 wildfire_mem_mask = 0; 211 212 memset(wildfire_hard_qbb_map, QBB_MAP_EMPTY, WILDFIRE_MAX_QBB); 213 memset(wildfire_soft_qbb_map, QBB_MAP_EMPTY, WILDFIRE_MAX_QBB); 214 215 /* First, determine which QBBs are present. */ 216 qsa = WILDFIRE_qsa(soft_qbb); 217 218 temp = qsa->qsa_qbb_id.csr; 219 #if 0 220 printk(KERN_ERR "QSA_QBB_ID at base %p is 0x%lx\n", qsa, temp); 221 #endif 222 223 if (temp & 0x40) /* Is there an HS? */ 224 wildfire_hs_mask = 1; 225 226 if (temp & 0x20) { /* Is there a GP? */ 227 gp = WILDFIRE_gp(soft_qbb); 228 temp = 0; 229 for (i = 0; i < 4; i++) { 230 temp |= gp->gpa_qbb_map[i].csr << (i * 8); 231 #if 0 232 printk(KERN_ERR "GPA_QBB_MAP[%d] at base %p is 0x%lx\n", 233 i, gp, temp); 234 #endif 235 } 236 237 for (hard_qbb = 0; hard_qbb < WILDFIRE_MAX_QBB; hard_qbb++) { 238 if (temp & 8) { /* Is there a QBB? */ 239 soft_qbb = temp & 7; 240 wildfire_hard_qbb_mask |= (1 << hard_qbb); 241 wildfire_soft_qbb_mask |= (1 << soft_qbb); 242 } 243 temp >>= 4; 244 } 245 wildfire_gp_mask = wildfire_soft_qbb_mask; 246 } 247 248 /* Next determine each QBBs resources. */ 249 for (soft_qbb = 0; soft_qbb < WILDFIRE_MAX_QBB; soft_qbb++) { 250 if (WILDFIRE_QBB_EXISTS(soft_qbb)) { 251 qsd = WILDFIRE_qsd(soft_qbb); 252 temp = qsd->qsd_whami.csr; 253 #if 0 254 printk(KERN_ERR "QSD_WHAMI at base %p is 0x%lx\n", qsd, temp); 255 #endif 256 hard_qbb = (temp >> 8) & 7; 257 wildfire_hard_qbb_map[hard_qbb] = soft_qbb; 258 wildfire_soft_qbb_map[soft_qbb] = hard_qbb; 259 260 qsa = WILDFIRE_qsa(soft_qbb); 261 temp = qsa->qsa_qbb_pop[0].csr; 262 #if 0 263 printk(KERN_ERR "QSA_QBB_POP_0 at base %p is 0x%lx\n", qsa, temp); 264 #endif 265 wildfire_cpu_mask |= ((temp >> 0) & 0xf) << (soft_qbb << 2); 266 wildfire_mem_mask |= ((temp >> 4) & 0xf) << (soft_qbb << 2); 267 268 temp = qsa->qsa_qbb_pop[1].csr; 269 #if 0 270 printk(KERN_ERR "QSA_QBB_POP_1 at base %p is 0x%lx\n", qsa, temp); 271 #endif 272 wildfire_iop_mask |= (1 << soft_qbb); 273 wildfire_ior_mask |= ((temp >> 4) & 0xf) << (soft_qbb << 2); 274 275 temp = qsa->qsa_qbb_id.csr; 276 #if 0 277 printk(KERN_ERR "QSA_QBB_ID at %p is 0x%lx\n", qsa, temp); 278 #endif 279 if (temp & 0x20) 280 wildfire_gp_mask |= (1 << soft_qbb); 281 282 /* Probe for PCA existence here. */ 283 for (i = 0; i < WILDFIRE_PCA_PER_QBB; i++) { 284 iop = WILDFIRE_iop(soft_qbb); 285 ne = WILDFIRE_ne(soft_qbb, i); 286 fe = WILDFIRE_fe(soft_qbb, i); 287 288 if ((iop->iop_hose[i].init.csr & 1) == 1 && 289 ((ne->ne_what_am_i.csr & 0xf00000300UL) == 0x100000300UL) && 290 ((fe->fe_what_am_i.csr & 0xf00000300UL) == 0x100000200UL)) 291 { 292 wildfire_pca_mask |= 1 << ((soft_qbb << 2) + i); 293 } 294 } 295 296 } 297 } 298 #if DEBUG_DUMP_CONFIG 299 wildfire_dump_hardware_config(); 300 #endif 301 } 302 303 void __init 304 wildfire_init_arch(void) 305 { 306 int qbbno; 307 308 /* With multiple PCI buses, we play with I/O as physical addrs. */ 309 ioport_resource.end = ~0UL; 310 311 312 /* Probe the hardware for info about configuration. */ 313 wildfire_hardware_probe(); 314 315 /* Now init all the found QBBs. */ 316 for (qbbno = 0; qbbno < WILDFIRE_MAX_QBB; qbbno++) { 317 wildfire_init_qbb(qbbno); 318 } 319 320 /* Normal direct PCI DMA mapping. */ 321 __direct_map_base = 0x40000000UL; 322 __direct_map_size = 0x80000000UL; 323 } 324 325 void 326 wildfire_machine_check(unsigned long vector, unsigned long la_ptr) 327 { 328 mb(); 329 mb(); /* magic */ 330 draina(); 331 /* FIXME: clear pci errors */ 332 wrmces(0x7); 333 mb(); 334 335 process_mcheck_info(vector, la_ptr, "WILDFIRE", 336 mcheck_expected(smp_processor_id())); 337 } 338 339 void 340 wildfire_kill_arch(int mode) 341 { 342 } 343 344 void 345 wildfire_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end) 346 { 347 int qbbno = hose->index >> 3; 348 int hoseno = hose->index & 7; 349 wildfire_pci *pci = WILDFIRE_pci(qbbno, hoseno); 350 351 mb(); 352 pci->pci_flush_tlb.csr; /* reading does the trick */ 353 } 354 355 static int 356 mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where, 357 unsigned long *pci_addr, unsigned char *type1) 358 { 359 struct pci_controller *hose = pbus->sysdata; 360 unsigned long addr; 361 u8 bus = pbus->number; 362 363 DBG_CFG(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x, " 364 "pci_addr=0x%p, type1=0x%p)\n", 365 bus, device_fn, where, pci_addr, type1)); 366 367 if (!pbus->parent) /* No parent means peer PCI bus. */ 368 bus = 0; 369 *type1 = (bus != 0); 370 371 addr = (bus << 16) | (device_fn << 8) | where; 372 addr |= hose->config_space_base; 373 374 *pci_addr = addr; 375 DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr)); 376 return 0; 377 } 378 379 static int 380 wildfire_read_config(struct pci_bus *bus, unsigned int devfn, int where, 381 int size, u32 *value) 382 { 383 unsigned long addr; 384 unsigned char type1; 385 386 if (mk_conf_addr(bus, devfn, where, &addr, &type1)) 387 return PCIBIOS_DEVICE_NOT_FOUND; 388 389 switch (size) { 390 case 1: 391 *value = __kernel_ldbu(*(vucp)addr); 392 break; 393 case 2: 394 *value = __kernel_ldwu(*(vusp)addr); 395 break; 396 case 4: 397 *value = *(vuip)addr; 398 break; 399 } 400 401 return PCIBIOS_SUCCESSFUL; 402 } 403 404 static int 405 wildfire_write_config(struct pci_bus *bus, unsigned int devfn, int where, 406 int size, u32 value) 407 { 408 unsigned long addr; 409 unsigned char type1; 410 411 if (mk_conf_addr(bus, devfn, where, &addr, &type1)) 412 return PCIBIOS_DEVICE_NOT_FOUND; 413 414 switch (size) { 415 case 1: 416 __kernel_stb(value, *(vucp)addr); 417 mb(); 418 __kernel_ldbu(*(vucp)addr); 419 break; 420 case 2: 421 __kernel_stw(value, *(vusp)addr); 422 mb(); 423 __kernel_ldwu(*(vusp)addr); 424 break; 425 case 4: 426 *(vuip)addr = value; 427 mb(); 428 *(vuip)addr; 429 break; 430 } 431 432 return PCIBIOS_SUCCESSFUL; 433 } 434 435 struct pci_ops wildfire_pci_ops = 436 { 437 .read = wildfire_read_config, 438 .write = wildfire_write_config, 439 }; 440 441 442 /* 443 * NUMA Support 444 */ 445 int wildfire_pa_to_nid(unsigned long pa) 446 { 447 return pa >> 36; 448 } 449 450 int wildfire_cpuid_to_nid(int cpuid) 451 { 452 /* assume 4 CPUs per node */ 453 return cpuid >> 2; 454 } 455 456 unsigned long wildfire_node_mem_start(int nid) 457 { 458 /* 64GB per node */ 459 return (unsigned long)nid * (64UL * 1024 * 1024 * 1024); 460 } 461 462 unsigned long wildfire_node_mem_size(int nid) 463 { 464 /* 64GB per node */ 465 return 64UL * 1024 * 1024 * 1024; 466 } 467 468 #if DEBUG_DUMP_REGS 469 470 static void __init 471 wildfire_dump_pci_regs(int qbbno, int hoseno) 472 { 473 wildfire_pci *pci = WILDFIRE_pci(qbbno, hoseno); 474 int i; 475 476 printk(KERN_ERR "PCI registers for QBB %d hose %d (%p)\n", 477 qbbno, hoseno, pci); 478 479 printk(KERN_ERR " PCI_IO_ADDR_EXT: 0x%16lx\n", 480 pci->pci_io_addr_ext.csr); 481 printk(KERN_ERR " PCI_CTRL: 0x%16lx\n", pci->pci_ctrl.csr); 482 printk(KERN_ERR " PCI_ERR_SUM: 0x%16lx\n", pci->pci_err_sum.csr); 483 printk(KERN_ERR " PCI_ERR_ADDR: 0x%16lx\n", pci->pci_err_addr.csr); 484 printk(KERN_ERR " PCI_STALL_CNT: 0x%16lx\n", pci->pci_stall_cnt.csr); 485 printk(KERN_ERR " PCI_PEND_INT: 0x%16lx\n", pci->pci_pend_int.csr); 486 printk(KERN_ERR " PCI_SENT_INT: 0x%16lx\n", pci->pci_sent_int.csr); 487 488 printk(KERN_ERR " DMA window registers for QBB %d hose %d (%p)\n", 489 qbbno, hoseno, pci); 490 for (i = 0; i < 4; i++) { 491 printk(KERN_ERR " window %d: 0x%16lx 0x%16lx 0x%16lx\n", i, 492 pci->pci_window[i].wbase.csr, 493 pci->pci_window[i].wmask.csr, 494 pci->pci_window[i].tbase.csr); 495 } 496 printk(KERN_ERR "\n"); 497 } 498 499 static void __init 500 wildfire_dump_pca_regs(int qbbno, int pcano) 501 { 502 wildfire_pca *pca = WILDFIRE_pca(qbbno, pcano); 503 int i; 504 505 printk(KERN_ERR "PCA registers for QBB %d PCA %d (%p)\n", 506 qbbno, pcano, pca); 507 508 printk(KERN_ERR " PCA_WHAT_AM_I: 0x%16lx\n", pca->pca_what_am_i.csr); 509 printk(KERN_ERR " PCA_ERR_SUM: 0x%16lx\n", pca->pca_err_sum.csr); 510 printk(KERN_ERR " PCA_PEND_INT: 0x%16lx\n", pca->pca_pend_int.csr); 511 printk(KERN_ERR " PCA_SENT_INT: 0x%16lx\n", pca->pca_sent_int.csr); 512 printk(KERN_ERR " PCA_STDIO_EL: 0x%16lx\n", 513 pca->pca_stdio_edge_level.csr); 514 515 printk(KERN_ERR " PCA target registers for QBB %d PCA %d (%p)\n", 516 qbbno, pcano, pca); 517 for (i = 0; i < 4; i++) { 518 printk(KERN_ERR " target %d: 0x%16lx 0x%16lx\n", i, 519 pca->pca_int[i].target.csr, 520 pca->pca_int[i].enable.csr); 521 } 522 523 printk(KERN_ERR "\n"); 524 } 525 526 static void __init 527 wildfire_dump_qsa_regs(int qbbno) 528 { 529 wildfire_qsa *qsa = WILDFIRE_qsa(qbbno); 530 int i; 531 532 printk(KERN_ERR "QSA registers for QBB %d (%p)\n", qbbno, qsa); 533 534 printk(KERN_ERR " QSA_QBB_ID: 0x%16lx\n", qsa->qsa_qbb_id.csr); 535 printk(KERN_ERR " QSA_PORT_ENA: 0x%16lx\n", qsa->qsa_port_ena.csr); 536 printk(KERN_ERR " QSA_REF_INT: 0x%16lx\n", qsa->qsa_ref_int.csr); 537 538 for (i = 0; i < 5; i++) 539 printk(KERN_ERR " QSA_CONFIG_%d: 0x%16lx\n", 540 i, qsa->qsa_config[i].csr); 541 542 for (i = 0; i < 2; i++) 543 printk(KERN_ERR " QSA_QBB_POP_%d: 0x%16lx\n", 544 i, qsa->qsa_qbb_pop[0].csr); 545 546 printk(KERN_ERR "\n"); 547 } 548 549 static void __init 550 wildfire_dump_qsd_regs(int qbbno) 551 { 552 wildfire_qsd *qsd = WILDFIRE_qsd(qbbno); 553 554 printk(KERN_ERR "QSD registers for QBB %d (%p)\n", qbbno, qsd); 555 556 printk(KERN_ERR " QSD_WHAMI: 0x%16lx\n", qsd->qsd_whami.csr); 557 printk(KERN_ERR " QSD_REV: 0x%16lx\n", qsd->qsd_rev.csr); 558 printk(KERN_ERR " QSD_PORT_PRESENT: 0x%16lx\n", 559 qsd->qsd_port_present.csr); 560 printk(KERN_ERR " QSD_PORT_ACTUVE: 0x%16lx\n", 561 qsd->qsd_port_active.csr); 562 printk(KERN_ERR " QSD_FAULT_ENA: 0x%16lx\n", 563 qsd->qsd_fault_ena.csr); 564 printk(KERN_ERR " QSD_CPU_INT_ENA: 0x%16lx\n", 565 qsd->qsd_cpu_int_ena.csr); 566 printk(KERN_ERR " QSD_MEM_CONFIG: 0x%16lx\n", 567 qsd->qsd_mem_config.csr); 568 printk(KERN_ERR " QSD_ERR_SUM: 0x%16lx\n", 569 qsd->qsd_err_sum.csr); 570 571 printk(KERN_ERR "\n"); 572 } 573 574 static void __init 575 wildfire_dump_iop_regs(int qbbno) 576 { 577 wildfire_iop *iop = WILDFIRE_iop(qbbno); 578 int i; 579 580 printk(KERN_ERR "IOP registers for QBB %d (%p)\n", qbbno, iop); 581 582 printk(KERN_ERR " IOA_CONFIG: 0x%16lx\n", iop->ioa_config.csr); 583 printk(KERN_ERR " IOD_CONFIG: 0x%16lx\n", iop->iod_config.csr); 584 printk(KERN_ERR " IOP_SWITCH_CREDITS: 0x%16lx\n", 585 iop->iop_switch_credits.csr); 586 printk(KERN_ERR " IOP_HOSE_CREDITS: 0x%16lx\n", 587 iop->iop_hose_credits.csr); 588 589 for (i = 0; i < 4; i++) 590 printk(KERN_ERR " IOP_HOSE_%d_INIT: 0x%16lx\n", 591 i, iop->iop_hose[i].init.csr); 592 for (i = 0; i < 4; i++) 593 printk(KERN_ERR " IOP_DEV_INT_TARGET_%d: 0x%16lx\n", 594 i, iop->iop_dev_int[i].target.csr); 595 596 printk(KERN_ERR "\n"); 597 } 598 599 static void __init 600 wildfire_dump_gp_regs(int qbbno) 601 { 602 wildfire_gp *gp = WILDFIRE_gp(qbbno); 603 int i; 604 605 printk(KERN_ERR "GP registers for QBB %d (%p)\n", qbbno, gp); 606 for (i = 0; i < 4; i++) 607 printk(KERN_ERR " GPA_QBB_MAP_%d: 0x%16lx\n", 608 i, gp->gpa_qbb_map[i].csr); 609 610 printk(KERN_ERR " GPA_MEM_POP_MAP: 0x%16lx\n", 611 gp->gpa_mem_pop_map.csr); 612 printk(KERN_ERR " GPA_SCRATCH: 0x%16lx\n", gp->gpa_scratch.csr); 613 printk(KERN_ERR " GPA_DIAG: 0x%16lx\n", gp->gpa_diag.csr); 614 printk(KERN_ERR " GPA_CONFIG_0: 0x%16lx\n", gp->gpa_config_0.csr); 615 printk(KERN_ERR " GPA_INIT_ID: 0x%16lx\n", gp->gpa_init_id.csr); 616 printk(KERN_ERR " GPA_CONFIG_2: 0x%16lx\n", gp->gpa_config_2.csr); 617 618 printk(KERN_ERR "\n"); 619 } 620 #endif /* DUMP_REGS */ 621 622 #if DEBUG_DUMP_CONFIG 623 static void __init 624 wildfire_dump_hardware_config(void) 625 { 626 int i; 627 628 printk(KERN_ERR "Probed Hardware Configuration\n"); 629 630 printk(KERN_ERR " hard_qbb_mask: 0x%16lx\n", wildfire_hard_qbb_mask); 631 printk(KERN_ERR " soft_qbb_mask: 0x%16lx\n", wildfire_soft_qbb_mask); 632 633 printk(KERN_ERR " gp_mask: 0x%16lx\n", wildfire_gp_mask); 634 printk(KERN_ERR " hs_mask: 0x%16lx\n", wildfire_hs_mask); 635 printk(KERN_ERR " iop_mask: 0x%16lx\n", wildfire_iop_mask); 636 printk(KERN_ERR " ior_mask: 0x%16lx\n", wildfire_ior_mask); 637 printk(KERN_ERR " pca_mask: 0x%16lx\n", wildfire_pca_mask); 638 639 printk(KERN_ERR " cpu_mask: 0x%16lx\n", wildfire_cpu_mask); 640 printk(KERN_ERR " mem_mask: 0x%16lx\n", wildfire_mem_mask); 641 642 printk(" hard_qbb_map: "); 643 for (i = 0; i < WILDFIRE_MAX_QBB; i++) 644 if (wildfire_hard_qbb_map[i] == QBB_MAP_EMPTY) 645 printk("--- "); 646 else 647 printk("%3d ", wildfire_hard_qbb_map[i]); 648 printk("\n"); 649 650 printk(" soft_qbb_map: "); 651 for (i = 0; i < WILDFIRE_MAX_QBB; i++) 652 if (wildfire_soft_qbb_map[i] == QBB_MAP_EMPTY) 653 printk("--- "); 654 else 655 printk("%3d ", wildfire_soft_qbb_map[i]); 656 printk("\n"); 657 } 658 #endif /* DUMP_CONFIG */ 659