1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * linux/arch/alpha/kernel/core_titan.c 4 * 5 * Code common to all TITAN core logic chips. 6 */ 7 8 #define __EXTERN_INLINE inline 9 #include <asm/io.h> 10 #include <asm/core_titan.h> 11 #undef __EXTERN_INLINE 12 13 #include <linux/module.h> 14 #include <linux/types.h> 15 #include <linux/pci.h> 16 #include <linux/sched.h> 17 #include <linux/init.h> 18 #include <linux/vmalloc.h> 19 #include <linux/bootmem.h> 20 21 #include <asm/ptrace.h> 22 #include <asm/smp.h> 23 #include <asm/pgalloc.h> 24 #include <asm/tlbflush.h> 25 #include <asm/vga.h> 26 27 #include "proto.h" 28 #include "pci_impl.h" 29 30 /* Save Titan configuration data as the console had it set up. */ 31 32 struct 33 { 34 unsigned long wsba[4]; 35 unsigned long wsm[4]; 36 unsigned long tba[4]; 37 } saved_config[4] __attribute__((common)); 38 39 /* 40 * Is PChip 1 present? No need to query it more than once. 41 */ 42 static int titan_pchip1_present; 43 44 /* 45 * BIOS32-style PCI interface: 46 */ 47 48 #define DEBUG_CONFIG 0 49 50 #if DEBUG_CONFIG 51 # define DBG_CFG(args) printk args 52 #else 53 # define DBG_CFG(args) 54 #endif 55 56 57 /* 58 * Routines to access TIG registers. 59 */ 60 static inline volatile unsigned long * 61 mk_tig_addr(int offset) 62 { 63 return (volatile unsigned long *)(TITAN_TIG_SPACE + (offset << 6)); 64 } 65 66 static inline u8 67 titan_read_tig(int offset, u8 value) 68 { 69 volatile unsigned long *tig_addr = mk_tig_addr(offset); 70 return (u8)(*tig_addr & 0xff); 71 } 72 73 static inline void 74 titan_write_tig(int offset, u8 value) 75 { 76 volatile unsigned long *tig_addr = mk_tig_addr(offset); 77 *tig_addr = (unsigned long)value; 78 } 79 80 81 /* 82 * Given a bus, device, and function number, compute resulting 83 * configuration space address 84 * accordingly. It is therefore not safe to have concurrent 85 * invocations to configuration space access routines, but there 86 * really shouldn't be any need for this. 87 * 88 * Note that all config space accesses use Type 1 address format. 89 * 90 * Note also that type 1 is determined by non-zero bus number. 91 * 92 * Type 1: 93 * 94 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 95 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 96 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 97 * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1| 98 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 99 * 100 * 31:24 reserved 101 * 23:16 bus number (8 bits = 128 possible buses) 102 * 15:11 Device number (5 bits) 103 * 10:8 function number 104 * 7:2 register number 105 * 106 * Notes: 107 * The function number selects which function of a multi-function device 108 * (e.g., SCSI and Ethernet). 109 * 110 * The register selects a DWORD (32 bit) register offset. Hence it 111 * doesn't get shifted by 2 bits as we want to "drop" the bottom two 112 * bits. 113 */ 114 115 static int 116 mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where, 117 unsigned long *pci_addr, unsigned char *type1) 118 { 119 struct pci_controller *hose = pbus->sysdata; 120 unsigned long addr; 121 u8 bus = pbus->number; 122 123 DBG_CFG(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x, " 124 "pci_addr=0x%p, type1=0x%p)\n", 125 bus, device_fn, where, pci_addr, type1)); 126 127 if (!pbus->parent) /* No parent means peer PCI bus. */ 128 bus = 0; 129 *type1 = (bus != 0); 130 131 addr = (bus << 16) | (device_fn << 8) | where; 132 addr |= hose->config_space_base; 133 134 *pci_addr = addr; 135 DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr)); 136 return 0; 137 } 138 139 static int 140 titan_read_config(struct pci_bus *bus, unsigned int devfn, int where, 141 int size, u32 *value) 142 { 143 unsigned long addr; 144 unsigned char type1; 145 146 if (mk_conf_addr(bus, devfn, where, &addr, &type1)) 147 return PCIBIOS_DEVICE_NOT_FOUND; 148 149 switch (size) { 150 case 1: 151 *value = __kernel_ldbu(*(vucp)addr); 152 break; 153 case 2: 154 *value = __kernel_ldwu(*(vusp)addr); 155 break; 156 case 4: 157 *value = *(vuip)addr; 158 break; 159 } 160 161 return PCIBIOS_SUCCESSFUL; 162 } 163 164 static int 165 titan_write_config(struct pci_bus *bus, unsigned int devfn, int where, 166 int size, u32 value) 167 { 168 unsigned long addr; 169 unsigned char type1; 170 171 if (mk_conf_addr(bus, devfn, where, &addr, &type1)) 172 return PCIBIOS_DEVICE_NOT_FOUND; 173 174 switch (size) { 175 case 1: 176 __kernel_stb(value, *(vucp)addr); 177 mb(); 178 __kernel_ldbu(*(vucp)addr); 179 break; 180 case 2: 181 __kernel_stw(value, *(vusp)addr); 182 mb(); 183 __kernel_ldwu(*(vusp)addr); 184 break; 185 case 4: 186 *(vuip)addr = value; 187 mb(); 188 *(vuip)addr; 189 break; 190 } 191 192 return PCIBIOS_SUCCESSFUL; 193 } 194 195 struct pci_ops titan_pci_ops = 196 { 197 .read = titan_read_config, 198 .write = titan_write_config, 199 }; 200 201 202 void 203 titan_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end) 204 { 205 titan_pachip *pachip = 206 (hose->index & 1) ? TITAN_pachip1 : TITAN_pachip0; 207 titan_pachip_port *port; 208 volatile unsigned long *csr; 209 unsigned long value; 210 211 /* Get the right hose. */ 212 port = &pachip->g_port; 213 if (hose->index & 2) 214 port = &pachip->a_port; 215 216 /* We can invalidate up to 8 tlb entries in a go. The flush 217 matches against <31:16> in the pci address. 218 Note that gtlbi* and atlbi* are in the same place in the g_port 219 and a_port, respectively, so the g_port offset can be used 220 even if hose is an a_port */ 221 csr = &port->port_specific.g.gtlbia.csr; 222 if (((start ^ end) & 0xffff0000) == 0) 223 csr = &port->port_specific.g.gtlbiv.csr; 224 225 /* For TBIA, it doesn't matter what value we write. For TBI, 226 it's the shifted tag bits. */ 227 value = (start & 0xffff0000) >> 12; 228 229 wmb(); 230 *csr = value; 231 mb(); 232 *csr; 233 } 234 235 static int 236 titan_query_agp(titan_pachip_port *port) 237 { 238 union TPAchipPCTL pctl; 239 240 /* set up APCTL */ 241 pctl.pctl_q_whole = port->pctl.csr; 242 243 return pctl.pctl_r_bits.apctl_v_agp_present; 244 245 } 246 247 static void __init 248 titan_init_one_pachip_port(titan_pachip_port *port, int index) 249 { 250 struct pci_controller *hose; 251 252 hose = alloc_pci_controller(); 253 if (index == 0) 254 pci_isa_hose = hose; 255 hose->io_space = alloc_resource(); 256 hose->mem_space = alloc_resource(); 257 258 /* 259 * This is for userland consumption. The 40-bit PIO bias that we 260 * use in the kernel through KSEG doesn't work in the page table 261 * based user mappings. (43-bit KSEG sign extends the physical 262 * address from bit 40 to hit the I/O bit - mapped addresses don't). 263 * So make sure we get the 43-bit PIO bias. 264 */ 265 hose->sparse_mem_base = 0; 266 hose->sparse_io_base = 0; 267 hose->dense_mem_base 268 = (TITAN_MEM(index) & 0xffffffffffUL) | 0x80000000000UL; 269 hose->dense_io_base 270 = (TITAN_IO(index) & 0xffffffffffUL) | 0x80000000000UL; 271 272 hose->config_space_base = TITAN_CONF(index); 273 hose->index = index; 274 275 hose->io_space->start = TITAN_IO(index) - TITAN_IO_BIAS; 276 hose->io_space->end = hose->io_space->start + TITAN_IO_SPACE - 1; 277 hose->io_space->name = pci_io_names[index]; 278 hose->io_space->flags = IORESOURCE_IO; 279 280 hose->mem_space->start = TITAN_MEM(index) - TITAN_MEM_BIAS; 281 hose->mem_space->end = hose->mem_space->start + 0xffffffff; 282 hose->mem_space->name = pci_mem_names[index]; 283 hose->mem_space->flags = IORESOURCE_MEM; 284 285 if (request_resource(&ioport_resource, hose->io_space) < 0) 286 printk(KERN_ERR "Failed to request IO on hose %d\n", index); 287 if (request_resource(&iomem_resource, hose->mem_space) < 0) 288 printk(KERN_ERR "Failed to request MEM on hose %d\n", index); 289 290 /* 291 * Save the existing PCI window translations. SRM will 292 * need them when we go to reboot. 293 */ 294 saved_config[index].wsba[0] = port->wsba[0].csr; 295 saved_config[index].wsm[0] = port->wsm[0].csr; 296 saved_config[index].tba[0] = port->tba[0].csr; 297 298 saved_config[index].wsba[1] = port->wsba[1].csr; 299 saved_config[index].wsm[1] = port->wsm[1].csr; 300 saved_config[index].tba[1] = port->tba[1].csr; 301 302 saved_config[index].wsba[2] = port->wsba[2].csr; 303 saved_config[index].wsm[2] = port->wsm[2].csr; 304 saved_config[index].tba[2] = port->tba[2].csr; 305 306 saved_config[index].wsba[3] = port->wsba[3].csr; 307 saved_config[index].wsm[3] = port->wsm[3].csr; 308 saved_config[index].tba[3] = port->tba[3].csr; 309 310 /* 311 * Set up the PCI to main memory translation windows. 312 * 313 * Note: Window 3 on Titan is Scatter-Gather ONLY. 314 * 315 * Window 0 is scatter-gather 8MB at 8MB (for isa) 316 * Window 1 is direct access 1GB at 2GB 317 * Window 2 is scatter-gather 1GB at 3GB 318 */ 319 hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, 0); 320 hose->sg_isa->align_entry = 8; /* 64KB for ISA */ 321 322 hose->sg_pci = iommu_arena_new(hose, 0xc0000000, 0x40000000, 0); 323 hose->sg_pci->align_entry = 4; /* Titan caches 4 PTEs at a time */ 324 325 port->wsba[0].csr = hose->sg_isa->dma_base | 3; 326 port->wsm[0].csr = (hose->sg_isa->size - 1) & 0xfff00000; 327 port->tba[0].csr = virt_to_phys(hose->sg_isa->ptes); 328 329 port->wsba[1].csr = __direct_map_base | 1; 330 port->wsm[1].csr = (__direct_map_size - 1) & 0xfff00000; 331 port->tba[1].csr = 0; 332 333 port->wsba[2].csr = hose->sg_pci->dma_base | 3; 334 port->wsm[2].csr = (hose->sg_pci->size - 1) & 0xfff00000; 335 port->tba[2].csr = virt_to_phys(hose->sg_pci->ptes); 336 337 port->wsba[3].csr = 0; 338 339 /* Enable the Monster Window to make DAC pci64 possible. */ 340 port->pctl.csr |= pctl_m_mwin; 341 342 /* 343 * If it's an AGP port, initialize agplastwr. 344 */ 345 if (titan_query_agp(port)) 346 port->port_specific.a.agplastwr.csr = __direct_map_base; 347 348 titan_pci_tbi(hose, 0, -1); 349 } 350 351 static void __init 352 titan_init_pachips(titan_pachip *pachip0, titan_pachip *pachip1) 353 { 354 titan_pchip1_present = TITAN_cchip->csc.csr & 1L<<14; 355 356 /* Init the ports in hose order... */ 357 titan_init_one_pachip_port(&pachip0->g_port, 0); /* hose 0 */ 358 if (titan_pchip1_present) 359 titan_init_one_pachip_port(&pachip1->g_port, 1);/* hose 1 */ 360 titan_init_one_pachip_port(&pachip0->a_port, 2); /* hose 2 */ 361 if (titan_pchip1_present) 362 titan_init_one_pachip_port(&pachip1->a_port, 3);/* hose 3 */ 363 } 364 365 void __init 366 titan_init_arch(void) 367 { 368 #if 0 369 printk("%s: titan_init_arch()\n", __func__); 370 printk("%s: CChip registers:\n", __func__); 371 printk("%s: CSR_CSC 0x%lx\n", __func__, TITAN_cchip->csc.csr); 372 printk("%s: CSR_MTR 0x%lx\n", __func__, TITAN_cchip->mtr.csr); 373 printk("%s: CSR_MISC 0x%lx\n", __func__, TITAN_cchip->misc.csr); 374 printk("%s: CSR_DIM0 0x%lx\n", __func__, TITAN_cchip->dim0.csr); 375 printk("%s: CSR_DIM1 0x%lx\n", __func__, TITAN_cchip->dim1.csr); 376 printk("%s: CSR_DIR0 0x%lx\n", __func__, TITAN_cchip->dir0.csr); 377 printk("%s: CSR_DIR1 0x%lx\n", __func__, TITAN_cchip->dir1.csr); 378 printk("%s: CSR_DRIR 0x%lx\n", __func__, TITAN_cchip->drir.csr); 379 380 printk("%s: DChip registers:\n", __func__); 381 printk("%s: CSR_DSC 0x%lx\n", __func__, TITAN_dchip->dsc.csr); 382 printk("%s: CSR_STR 0x%lx\n", __func__, TITAN_dchip->str.csr); 383 printk("%s: CSR_DREV 0x%lx\n", __func__, TITAN_dchip->drev.csr); 384 #endif 385 386 boot_cpuid = __hard_smp_processor_id(); 387 388 /* With multiple PCI busses, we play with I/O as physical addrs. */ 389 ioport_resource.end = ~0UL; 390 iomem_resource.end = ~0UL; 391 392 /* PCI DMA Direct Mapping is 1GB at 2GB. */ 393 __direct_map_base = 0x80000000; 394 __direct_map_size = 0x40000000; 395 396 /* Init the PA chip(s). */ 397 titan_init_pachips(TITAN_pachip0, TITAN_pachip1); 398 399 /* Check for graphic console location (if any). */ 400 find_console_vga_hose(); 401 } 402 403 static void 404 titan_kill_one_pachip_port(titan_pachip_port *port, int index) 405 { 406 port->wsba[0].csr = saved_config[index].wsba[0]; 407 port->wsm[0].csr = saved_config[index].wsm[0]; 408 port->tba[0].csr = saved_config[index].tba[0]; 409 410 port->wsba[1].csr = saved_config[index].wsba[1]; 411 port->wsm[1].csr = saved_config[index].wsm[1]; 412 port->tba[1].csr = saved_config[index].tba[1]; 413 414 port->wsba[2].csr = saved_config[index].wsba[2]; 415 port->wsm[2].csr = saved_config[index].wsm[2]; 416 port->tba[2].csr = saved_config[index].tba[2]; 417 418 port->wsba[3].csr = saved_config[index].wsba[3]; 419 port->wsm[3].csr = saved_config[index].wsm[3]; 420 port->tba[3].csr = saved_config[index].tba[3]; 421 } 422 423 static void 424 titan_kill_pachips(titan_pachip *pachip0, titan_pachip *pachip1) 425 { 426 if (titan_pchip1_present) { 427 titan_kill_one_pachip_port(&pachip1->g_port, 1); 428 titan_kill_one_pachip_port(&pachip1->a_port, 3); 429 } 430 titan_kill_one_pachip_port(&pachip0->g_port, 0); 431 titan_kill_one_pachip_port(&pachip0->a_port, 2); 432 } 433 434 void 435 titan_kill_arch(int mode) 436 { 437 titan_kill_pachips(TITAN_pachip0, TITAN_pachip1); 438 } 439 440 441 /* 442 * IO map support. 443 */ 444 445 void __iomem * 446 titan_ioportmap(unsigned long addr) 447 { 448 FIXUP_IOADDR_VGA(addr); 449 return (void __iomem *)(addr + TITAN_IO_BIAS); 450 } 451 452 453 void __iomem * 454 titan_ioremap(unsigned long addr, unsigned long size) 455 { 456 int h = (addr & TITAN_HOSE_MASK) >> TITAN_HOSE_SHIFT; 457 unsigned long baddr = addr & ~TITAN_HOSE_MASK; 458 unsigned long last = baddr + size - 1; 459 struct pci_controller *hose; 460 struct vm_struct *area; 461 unsigned long vaddr; 462 unsigned long *ptes; 463 unsigned long pfn; 464 465 #ifdef CONFIG_VGA_HOSE 466 /* 467 * Adjust the address and hose, if necessary. 468 */ 469 if (pci_vga_hose && __is_mem_vga(addr)) { 470 h = pci_vga_hose->index; 471 addr += pci_vga_hose->mem_space->start; 472 } 473 #endif 474 475 /* 476 * Find the hose. 477 */ 478 for (hose = hose_head; hose; hose = hose->next) 479 if (hose->index == h) 480 break; 481 if (!hose) 482 return NULL; 483 484 /* 485 * Is it direct-mapped? 486 */ 487 if ((baddr >= __direct_map_base) && 488 ((baddr + size - 1) < __direct_map_base + __direct_map_size)) { 489 vaddr = addr - __direct_map_base + TITAN_MEM_BIAS; 490 return (void __iomem *) vaddr; 491 } 492 493 /* 494 * Check the scatter-gather arena. 495 */ 496 if (hose->sg_pci && 497 baddr >= (unsigned long)hose->sg_pci->dma_base && 498 last < (unsigned long)hose->sg_pci->dma_base + hose->sg_pci->size){ 499 500 /* 501 * Adjust the limits (mappings must be page aligned) 502 */ 503 baddr -= hose->sg_pci->dma_base; 504 last -= hose->sg_pci->dma_base; 505 baddr &= PAGE_MASK; 506 size = PAGE_ALIGN(last) - baddr; 507 508 /* 509 * Map it 510 */ 511 area = get_vm_area(size, VM_IOREMAP); 512 if (!area) { 513 printk("ioremap failed... no vm_area...\n"); 514 return NULL; 515 } 516 517 ptes = hose->sg_pci->ptes; 518 for (vaddr = (unsigned long)area->addr; 519 baddr <= last; 520 baddr += PAGE_SIZE, vaddr += PAGE_SIZE) { 521 pfn = ptes[baddr >> PAGE_SHIFT]; 522 if (!(pfn & 1)) { 523 printk("ioremap failed... pte not valid...\n"); 524 vfree(area->addr); 525 return NULL; 526 } 527 pfn >>= 1; /* make it a true pfn */ 528 529 if (__alpha_remap_area_pages(vaddr, 530 pfn << PAGE_SHIFT, 531 PAGE_SIZE, 0)) { 532 printk("FAILED to remap_area_pages...\n"); 533 vfree(area->addr); 534 return NULL; 535 } 536 } 537 538 flush_tlb_all(); 539 540 vaddr = (unsigned long)area->addr + (addr & ~PAGE_MASK); 541 return (void __iomem *) vaddr; 542 } 543 544 /* Assume a legacy (read: VGA) address, and return appropriately. */ 545 return (void __iomem *)(addr + TITAN_MEM_BIAS); 546 } 547 548 void 549 titan_iounmap(volatile void __iomem *xaddr) 550 { 551 unsigned long addr = (unsigned long) xaddr; 552 if (addr >= VMALLOC_START) 553 vfree((void *)(PAGE_MASK & addr)); 554 } 555 556 int 557 titan_is_mmio(const volatile void __iomem *xaddr) 558 { 559 unsigned long addr = (unsigned long) xaddr; 560 561 if (addr >= VMALLOC_START) 562 return 1; 563 else 564 return (addr & 0x100000000UL) == 0; 565 } 566 567 #ifndef CONFIG_ALPHA_GENERIC 568 EXPORT_SYMBOL(titan_ioportmap); 569 EXPORT_SYMBOL(titan_ioremap); 570 EXPORT_SYMBOL(titan_iounmap); 571 EXPORT_SYMBOL(titan_is_mmio); 572 #endif 573 574 /* 575 * AGP GART Support. 576 */ 577 #include <linux/agp_backend.h> 578 #include <asm/agp_backend.h> 579 #include <linux/slab.h> 580 #include <linux/delay.h> 581 582 struct titan_agp_aperture { 583 struct pci_iommu_arena *arena; 584 long pg_start; 585 long pg_count; 586 }; 587 588 static int 589 titan_agp_setup(alpha_agp_info *agp) 590 { 591 struct titan_agp_aperture *aper; 592 593 if (!alpha_agpgart_size) 594 return -ENOMEM; 595 596 aper = kmalloc(sizeof(struct titan_agp_aperture), GFP_KERNEL); 597 if (aper == NULL) 598 return -ENOMEM; 599 600 aper->arena = agp->hose->sg_pci; 601 aper->pg_count = alpha_agpgart_size / PAGE_SIZE; 602 aper->pg_start = iommu_reserve(aper->arena, aper->pg_count, 603 aper->pg_count - 1); 604 if (aper->pg_start < 0) { 605 printk(KERN_ERR "Failed to reserve AGP memory\n"); 606 kfree(aper); 607 return -ENOMEM; 608 } 609 610 agp->aperture.bus_base = 611 aper->arena->dma_base + aper->pg_start * PAGE_SIZE; 612 agp->aperture.size = aper->pg_count * PAGE_SIZE; 613 agp->aperture.sysdata = aper; 614 615 return 0; 616 } 617 618 static void 619 titan_agp_cleanup(alpha_agp_info *agp) 620 { 621 struct titan_agp_aperture *aper = agp->aperture.sysdata; 622 int status; 623 624 status = iommu_release(aper->arena, aper->pg_start, aper->pg_count); 625 if (status == -EBUSY) { 626 printk(KERN_WARNING 627 "Attempted to release bound AGP memory - unbinding\n"); 628 iommu_unbind(aper->arena, aper->pg_start, aper->pg_count); 629 status = iommu_release(aper->arena, aper->pg_start, 630 aper->pg_count); 631 } 632 if (status < 0) 633 printk(KERN_ERR "Failed to release AGP memory\n"); 634 635 kfree(aper); 636 kfree(agp); 637 } 638 639 static int 640 titan_agp_configure(alpha_agp_info *agp) 641 { 642 union TPAchipPCTL pctl; 643 titan_pachip_port *port = agp->private; 644 pctl.pctl_q_whole = port->pctl.csr; 645 646 /* Side-Band Addressing? */ 647 pctl.pctl_r_bits.apctl_v_agp_sba_en = agp->mode.bits.sba; 648 649 /* AGP Rate? */ 650 pctl.pctl_r_bits.apctl_v_agp_rate = 0; /* 1x */ 651 if (agp->mode.bits.rate & 2) 652 pctl.pctl_r_bits.apctl_v_agp_rate = 1; /* 2x */ 653 #if 0 654 if (agp->mode.bits.rate & 4) 655 pctl.pctl_r_bits.apctl_v_agp_rate = 2; /* 4x */ 656 #endif 657 658 /* RQ Depth? */ 659 pctl.pctl_r_bits.apctl_v_agp_hp_rd = 2; 660 pctl.pctl_r_bits.apctl_v_agp_lp_rd = 7; 661 662 /* 663 * AGP Enable. 664 */ 665 pctl.pctl_r_bits.apctl_v_agp_en = agp->mode.bits.enable; 666 667 /* Tell the user. */ 668 printk("Enabling AGP: %dX%s\n", 669 1 << pctl.pctl_r_bits.apctl_v_agp_rate, 670 pctl.pctl_r_bits.apctl_v_agp_sba_en ? " - SBA" : ""); 671 672 /* Write it. */ 673 port->pctl.csr = pctl.pctl_q_whole; 674 675 /* And wait at least 5000 66MHz cycles (per Titan spec). */ 676 udelay(100); 677 678 return 0; 679 } 680 681 static int 682 titan_agp_bind_memory(alpha_agp_info *agp, off_t pg_start, struct agp_memory *mem) 683 { 684 struct titan_agp_aperture *aper = agp->aperture.sysdata; 685 return iommu_bind(aper->arena, aper->pg_start + pg_start, 686 mem->page_count, mem->pages); 687 } 688 689 static int 690 titan_agp_unbind_memory(alpha_agp_info *agp, off_t pg_start, struct agp_memory *mem) 691 { 692 struct titan_agp_aperture *aper = agp->aperture.sysdata; 693 return iommu_unbind(aper->arena, aper->pg_start + pg_start, 694 mem->page_count); 695 } 696 697 static unsigned long 698 titan_agp_translate(alpha_agp_info *agp, dma_addr_t addr) 699 { 700 struct titan_agp_aperture *aper = agp->aperture.sysdata; 701 unsigned long baddr = addr - aper->arena->dma_base; 702 unsigned long pte; 703 704 if (addr < agp->aperture.bus_base || 705 addr >= agp->aperture.bus_base + agp->aperture.size) { 706 printk("%s: addr out of range\n", __func__); 707 return -EINVAL; 708 } 709 710 pte = aper->arena->ptes[baddr >> PAGE_SHIFT]; 711 if (!(pte & 1)) { 712 printk("%s: pte not valid\n", __func__); 713 return -EINVAL; 714 } 715 716 return (pte >> 1) << PAGE_SHIFT; 717 } 718 719 struct alpha_agp_ops titan_agp_ops = 720 { 721 .setup = titan_agp_setup, 722 .cleanup = titan_agp_cleanup, 723 .configure = titan_agp_configure, 724 .bind = titan_agp_bind_memory, 725 .unbind = titan_agp_unbind_memory, 726 .translate = titan_agp_translate 727 }; 728 729 alpha_agp_info * 730 titan_agp_info(void) 731 { 732 alpha_agp_info *agp; 733 struct pci_controller *hose; 734 titan_pachip_port *port; 735 int hosenum = -1; 736 union TPAchipPCTL pctl; 737 738 /* 739 * Find the AGP port. 740 */ 741 port = &TITAN_pachip0->a_port; 742 if (titan_query_agp(port)) 743 hosenum = 2; 744 if (hosenum < 0 && 745 titan_pchip1_present && 746 titan_query_agp(port = &TITAN_pachip1->a_port)) 747 hosenum = 3; 748 749 /* 750 * Find the hose the port is on. 751 */ 752 for (hose = hose_head; hose; hose = hose->next) 753 if (hose->index == hosenum) 754 break; 755 756 if (!hose || !hose->sg_pci) 757 return NULL; 758 759 /* 760 * Allocate the info structure. 761 */ 762 agp = kmalloc(sizeof(*agp), GFP_KERNEL); 763 if (!agp) 764 return NULL; 765 766 /* 767 * Fill it in. 768 */ 769 agp->hose = hose; 770 agp->private = port; 771 agp->ops = &titan_agp_ops; 772 773 /* 774 * Aperture - not configured until ops.setup(). 775 * 776 * FIXME - should we go ahead and allocate it here? 777 */ 778 agp->aperture.bus_base = 0; 779 agp->aperture.size = 0; 780 agp->aperture.sysdata = NULL; 781 782 /* 783 * Capabilities. 784 */ 785 agp->capability.lw = 0; 786 agp->capability.bits.rate = 3; /* 2x, 1x */ 787 agp->capability.bits.sba = 1; 788 agp->capability.bits.rq = 7; /* 8 - 1 */ 789 790 /* 791 * Mode. 792 */ 793 pctl.pctl_q_whole = port->pctl.csr; 794 agp->mode.lw = 0; 795 agp->mode.bits.rate = 1 << pctl.pctl_r_bits.apctl_v_agp_rate; 796 agp->mode.bits.sba = pctl.pctl_r_bits.apctl_v_agp_sba_en; 797 agp->mode.bits.rq = 7; /* RQ Depth? */ 798 agp->mode.bits.enable = pctl.pctl_r_bits.apctl_v_agp_en; 799 800 return agp; 801 } 802