1 #ifndef __ALPHA_PCI_H 2 #define __ALPHA_PCI_H 3 4 #ifdef __KERNEL__ 5 6 #include <linux/spinlock.h> 7 #include <linux/dma-mapping.h> 8 #include <asm/scatterlist.h> 9 #include <asm/machvec.h> 10 11 /* 12 * The following structure is used to manage multiple PCI busses. 13 */ 14 15 struct pci_dev; 16 struct pci_bus; 17 struct resource; 18 struct pci_iommu_arena; 19 struct page; 20 21 /* A controller. Used to manage multiple PCI busses. */ 22 23 struct pci_controller { 24 struct pci_controller *next; 25 struct pci_bus *bus; 26 struct resource *io_space; 27 struct resource *mem_space; 28 29 /* The following are for reporting to userland. The invariant is 30 that if we report a BWX-capable dense memory, we do not report 31 a sparse memory at all, even if it exists. */ 32 unsigned long sparse_mem_base; 33 unsigned long dense_mem_base; 34 unsigned long sparse_io_base; 35 unsigned long dense_io_base; 36 37 /* This one's for the kernel only. It's in KSEG somewhere. */ 38 unsigned long config_space_base; 39 40 unsigned int index; 41 /* For compatibility with current (as of July 2003) pciutils 42 and XFree86. Eventually will be removed. */ 43 unsigned int need_domain_info; 44 45 struct pci_iommu_arena *sg_pci; 46 struct pci_iommu_arena *sg_isa; 47 48 void *sysdata; 49 }; 50 51 /* Override the logic in pci_scan_bus for skipping already-configured 52 bus numbers. */ 53 54 #define pcibios_assign_all_busses() 1 55 56 #define PCIBIOS_MIN_IO alpha_mv.min_io_address 57 #define PCIBIOS_MIN_MEM alpha_mv.min_mem_address 58 59 extern void pcibios_set_master(struct pci_dev *dev); 60 61 extern inline void pcibios_penalize_isa_irq(int irq, int active) 62 { 63 /* We don't do dynamic PCI IRQ allocation */ 64 } 65 66 /* IOMMU controls. */ 67 68 /* The PCI address space does not equal the physical memory address space. 69 The networking and block device layers use this boolean for bounce buffer 70 decisions. */ 71 #define PCI_DMA_BUS_IS_PHYS 0 72 73 /* Allocate and map kernel buffer using consistent mode DMA for PCI 74 device. Returns non-NULL cpu-view pointer to the buffer if 75 successful and sets *DMA_ADDRP to the pci side dma address as well, 76 else DMA_ADDRP is undefined. */ 77 78 extern void *__pci_alloc_consistent(struct pci_dev *, size_t, 79 dma_addr_t *, gfp_t); 80 static inline void * 81 pci_alloc_consistent(struct pci_dev *dev, size_t size, dma_addr_t *dma) 82 { 83 return __pci_alloc_consistent(dev, size, dma, GFP_ATOMIC); 84 } 85 86 /* Free and unmap a consistent DMA buffer. CPU_ADDR and DMA_ADDR must 87 be values that were returned from pci_alloc_consistent. SIZE must 88 be the same as what as passed into pci_alloc_consistent. 89 References to the memory and mappings associated with CPU_ADDR or 90 DMA_ADDR past this call are illegal. */ 91 92 extern void pci_free_consistent(struct pci_dev *, size_t, void *, dma_addr_t); 93 94 /* Map a single buffer of the indicate size for PCI DMA in streaming mode. 95 The 32-bit PCI bus mastering address to use is returned. Once the device 96 is given the dma address, the device owns this memory until either 97 pci_unmap_single or pci_dma_sync_single_for_cpu is performed. */ 98 99 extern dma_addr_t pci_map_single(struct pci_dev *, void *, size_t, int); 100 101 /* Likewise, but for a page instead of an address. */ 102 extern dma_addr_t pci_map_page(struct pci_dev *, struct page *, 103 unsigned long, size_t, int); 104 105 /* Test for pci_map_single or pci_map_page having generated an error. */ 106 107 static inline int 108 pci_dma_mapping_error(struct pci_dev *pdev, dma_addr_t dma_addr) 109 { 110 return dma_addr == 0; 111 } 112 113 /* Unmap a single streaming mode DMA translation. The DMA_ADDR and 114 SIZE must match what was provided for in a previous pci_map_single 115 call. All other usages are undefined. After this call, reads by 116 the cpu to the buffer are guaranteed to see whatever the device 117 wrote there. */ 118 119 extern void pci_unmap_single(struct pci_dev *, dma_addr_t, size_t, int); 120 extern void pci_unmap_page(struct pci_dev *, dma_addr_t, size_t, int); 121 122 /* pci_unmap_{single,page} is not a nop, thus... */ 123 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ 124 dma_addr_t ADDR_NAME; 125 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \ 126 __u32 LEN_NAME; 127 #define pci_unmap_addr(PTR, ADDR_NAME) \ 128 ((PTR)->ADDR_NAME) 129 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \ 130 (((PTR)->ADDR_NAME) = (VAL)) 131 #define pci_unmap_len(PTR, LEN_NAME) \ 132 ((PTR)->LEN_NAME) 133 #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ 134 (((PTR)->LEN_NAME) = (VAL)) 135 136 /* Map a set of buffers described by scatterlist in streaming mode for 137 PCI DMA. This is the scatter-gather version of the above 138 pci_map_single interface. Here the scatter gather list elements 139 are each tagged with the appropriate PCI dma address and length. 140 They are obtained via sg_dma_{address,length}(SG). 141 142 NOTE: An implementation may be able to use a smaller number of DMA 143 address/length pairs than there are SG table elements. (for 144 example via virtual mapping capabilities) The routine returns the 145 number of addr/length pairs actually used, at most nents. 146 147 Device ownership issues as mentioned above for pci_map_single are 148 the same here. */ 149 150 extern int pci_map_sg(struct pci_dev *, struct scatterlist *, int, int); 151 152 /* Unmap a set of streaming mode DMA translations. Again, cpu read 153 rules concerning calls here are the same as for pci_unmap_single() 154 above. */ 155 156 extern void pci_unmap_sg(struct pci_dev *, struct scatterlist *, int, int); 157 158 /* Make physical memory consistent for a single streaming mode DMA 159 translation after a transfer and device currently has ownership 160 of the buffer. 161 162 If you perform a pci_map_single() but wish to interrogate the 163 buffer using the cpu, yet do not wish to teardown the PCI dma 164 mapping, you must call this function before doing so. At the next 165 point you give the PCI dma address back to the card, you must first 166 perform a pci_dma_sync_for_device, and then the device again owns 167 the buffer. */ 168 169 static inline void 170 pci_dma_sync_single_for_cpu(struct pci_dev *dev, dma_addr_t dma_addr, 171 long size, int direction) 172 { 173 /* Nothing to do. */ 174 } 175 176 static inline void 177 pci_dma_sync_single_for_device(struct pci_dev *dev, dma_addr_t dma_addr, 178 size_t size, int direction) 179 { 180 /* Nothing to do. */ 181 } 182 183 /* Make physical memory consistent for a set of streaming mode DMA 184 translations after a transfer. The same as pci_dma_sync_single_* 185 but for a scatter-gather list, same rules and usage. */ 186 187 static inline void 188 pci_dma_sync_sg_for_cpu(struct pci_dev *dev, struct scatterlist *sg, 189 int nents, int direction) 190 { 191 /* Nothing to do. */ 192 } 193 194 static inline void 195 pci_dma_sync_sg_for_device(struct pci_dev *dev, struct scatterlist *sg, 196 int nents, int direction) 197 { 198 /* Nothing to do. */ 199 } 200 201 /* Return whether the given PCI device DMA address mask can 202 be supported properly. For example, if your device can 203 only drive the low 24-bits during PCI bus mastering, then 204 you would pass 0x00ffffff as the mask to this function. */ 205 206 extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask); 207 208 #ifdef CONFIG_PCI 209 static inline void pci_dma_burst_advice(struct pci_dev *pdev, 210 enum pci_dma_burst_strategy *strat, 211 unsigned long *strategy_parameter) 212 { 213 unsigned long cacheline_size; 214 u8 byte; 215 216 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte); 217 if (byte == 0) 218 cacheline_size = 1024; 219 else 220 cacheline_size = (int) byte * 4; 221 222 *strat = PCI_DMA_BURST_BOUNDARY; 223 *strategy_parameter = cacheline_size; 224 } 225 #endif 226 227 /* TODO: integrate with include/asm-generic/pci.h ? */ 228 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) 229 { 230 return channel ? 15 : 14; 231 } 232 233 extern void pcibios_resource_to_bus(struct pci_dev *, struct pci_bus_region *, 234 struct resource *); 235 236 extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 237 struct pci_bus_region *region); 238 239 #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index 240 241 static inline int pci_proc_domain(struct pci_bus *bus) 242 { 243 struct pci_controller *hose = bus->sysdata; 244 return hose->need_domain_info; 245 } 246 247 struct pci_dev *alpha_gendev_to_pci(struct device *dev); 248 249 #endif /* __KERNEL__ */ 250 251 /* Values for the `which' argument to sys_pciconfig_iobase. */ 252 #define IOBASE_HOSE 0 253 #define IOBASE_SPARSE_MEM 1 254 #define IOBASE_DENSE_MEM 2 255 #define IOBASE_SPARSE_IO 3 256 #define IOBASE_DENSE_IO 4 257 #define IOBASE_ROOT_BUS 5 258 #define IOBASE_FROM_HOSE 0x10000 259 260 extern struct pci_dev *isa_bridge; 261 262 extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, 263 size_t count); 264 extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, 265 size_t count); 266 extern int pci_mmap_legacy_page_range(struct pci_bus *bus, 267 struct vm_area_struct *vma, 268 enum pci_mmap_state mmap_state); 269 extern void pci_adjust_legacy_attr(struct pci_bus *bus, 270 enum pci_mmap_state mmap_type); 271 #define HAVE_PCI_LEGACY 1 272 273 extern int pci_create_resource_files(struct pci_dev *dev); 274 extern void pci_remove_resource_files(struct pci_dev *dev); 275 276 #endif /* __ALPHA_PCI_H */ 277