1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ALPHA_IO_H 3 #define __ALPHA_IO_H 4 5 #ifdef __KERNEL__ 6 7 #include <linux/kernel.h> 8 #include <linux/mm.h> 9 #include <asm/compiler.h> 10 #include <asm/pgtable.h> 11 #include <asm/machvec.h> 12 #include <asm/hwrpb.h> 13 14 /* The generic header contains only prototypes. Including it ensures that 15 the implementation we have here matches that interface. */ 16 #include <asm-generic/iomap.h> 17 18 /* We don't use IO slowdowns on the Alpha, but.. */ 19 #define __SLOW_DOWN_IO do { } while (0) 20 #define SLOW_DOWN_IO do { } while (0) 21 22 /* 23 * Virtual -> physical identity mapping starts at this offset 24 */ 25 #ifdef USE_48_BIT_KSEG 26 #define IDENT_ADDR 0xffff800000000000UL 27 #else 28 #define IDENT_ADDR 0xfffffc0000000000UL 29 #endif 30 31 /* 32 * We try to avoid hae updates (thus the cache), but when we 33 * do need to update the hae, we need to do it atomically, so 34 * that any interrupts wouldn't get confused with the hae 35 * register not being up-to-date with respect to the hardware 36 * value. 37 */ 38 extern inline void __set_hae(unsigned long new_hae) 39 { 40 unsigned long flags = swpipl(IPL_MAX); 41 42 barrier(); 43 44 alpha_mv.hae_cache = new_hae; 45 *alpha_mv.hae_register = new_hae; 46 mb(); 47 /* Re-read to make sure it was written. */ 48 new_hae = *alpha_mv.hae_register; 49 50 setipl(flags); 51 barrier(); 52 } 53 54 extern inline void set_hae(unsigned long new_hae) 55 { 56 if (new_hae != alpha_mv.hae_cache) 57 __set_hae(new_hae); 58 } 59 60 /* 61 * Change virtual addresses to physical addresses and vv. 62 */ 63 #ifdef USE_48_BIT_KSEG 64 static inline unsigned long virt_to_phys(void *address) 65 { 66 return (unsigned long)address - IDENT_ADDR; 67 } 68 69 static inline void * phys_to_virt(unsigned long address) 70 { 71 return (void *) (address + IDENT_ADDR); 72 } 73 #else 74 static inline unsigned long virt_to_phys(void *address) 75 { 76 unsigned long phys = (unsigned long)address; 77 78 /* Sign-extend from bit 41. */ 79 phys <<= (64 - 41); 80 phys = (long)phys >> (64 - 41); 81 82 /* Crop to the physical address width of the processor. */ 83 phys &= (1ul << hwrpb->pa_bits) - 1; 84 85 return phys; 86 } 87 88 static inline void * phys_to_virt(unsigned long address) 89 { 90 return (void *)(IDENT_ADDR + (address & ((1ul << 41) - 1))); 91 } 92 #endif 93 94 #define page_to_phys(page) page_to_pa(page) 95 96 static inline dma_addr_t __deprecated isa_page_to_bus(struct page *page) 97 { 98 return page_to_phys(page); 99 } 100 101 /* Maximum PIO space address supported? */ 102 #define IO_SPACE_LIMIT 0xffff 103 104 /* 105 * Change addresses as seen by the kernel (virtual) to addresses as 106 * seen by a device (bus), and vice versa. 107 * 108 * Note that this only works for a limited range of kernel addresses, 109 * and very well may not span all memory. Consider this interface 110 * deprecated in favour of the DMA-mapping API. 111 */ 112 extern unsigned long __direct_map_base; 113 extern unsigned long __direct_map_size; 114 115 static inline unsigned long __deprecated virt_to_bus(void *address) 116 { 117 unsigned long phys = virt_to_phys(address); 118 unsigned long bus = phys + __direct_map_base; 119 return phys <= __direct_map_size ? bus : 0; 120 } 121 #define isa_virt_to_bus virt_to_bus 122 123 static inline void * __deprecated bus_to_virt(unsigned long address) 124 { 125 void *virt; 126 127 /* This check is a sanity check but also ensures that bus address 0 128 maps to virtual address 0 which is useful to detect null pointers 129 (the NCR driver is much simpler if NULL pointers are preserved). */ 130 address -= __direct_map_base; 131 virt = phys_to_virt(address); 132 return (long)address <= 0 ? NULL : virt; 133 } 134 #define isa_bus_to_virt bus_to_virt 135 136 /* 137 * There are different chipsets to interface the Alpha CPUs to the world. 138 */ 139 140 #define IO_CONCAT(a,b) _IO_CONCAT(a,b) 141 #define _IO_CONCAT(a,b) a ## _ ## b 142 143 #ifdef CONFIG_ALPHA_GENERIC 144 145 /* In a generic kernel, we always go through the machine vector. */ 146 147 #define REMAP1(TYPE, NAME, QUAL) \ 148 static inline TYPE generic_##NAME(QUAL void __iomem *addr) \ 149 { \ 150 return alpha_mv.mv_##NAME(addr); \ 151 } 152 153 #define REMAP2(TYPE, NAME, QUAL) \ 154 static inline void generic_##NAME(TYPE b, QUAL void __iomem *addr) \ 155 { \ 156 alpha_mv.mv_##NAME(b, addr); \ 157 } 158 159 REMAP1(unsigned int, ioread8, /**/) 160 REMAP1(unsigned int, ioread16, /**/) 161 REMAP1(unsigned int, ioread32, /**/) 162 REMAP1(u8, readb, const volatile) 163 REMAP1(u16, readw, const volatile) 164 REMAP1(u32, readl, const volatile) 165 REMAP1(u64, readq, const volatile) 166 167 REMAP2(u8, iowrite8, /**/) 168 REMAP2(u16, iowrite16, /**/) 169 REMAP2(u32, iowrite32, /**/) 170 REMAP2(u8, writeb, volatile) 171 REMAP2(u16, writew, volatile) 172 REMAP2(u32, writel, volatile) 173 REMAP2(u64, writeq, volatile) 174 175 #undef REMAP1 176 #undef REMAP2 177 178 extern inline void __iomem *generic_ioportmap(unsigned long a) 179 { 180 return alpha_mv.mv_ioportmap(a); 181 } 182 183 static inline void __iomem *generic_ioremap(unsigned long a, unsigned long s) 184 { 185 return alpha_mv.mv_ioremap(a, s); 186 } 187 188 static inline void generic_iounmap(volatile void __iomem *a) 189 { 190 return alpha_mv.mv_iounmap(a); 191 } 192 193 static inline int generic_is_ioaddr(unsigned long a) 194 { 195 return alpha_mv.mv_is_ioaddr(a); 196 } 197 198 static inline int generic_is_mmio(const volatile void __iomem *a) 199 { 200 return alpha_mv.mv_is_mmio(a); 201 } 202 203 #define __IO_PREFIX generic 204 #define generic_trivial_rw_bw 0 205 #define generic_trivial_rw_lq 0 206 #define generic_trivial_io_bw 0 207 #define generic_trivial_io_lq 0 208 #define generic_trivial_iounmap 0 209 210 #else 211 212 #if defined(CONFIG_ALPHA_APECS) 213 # include <asm/core_apecs.h> 214 #elif defined(CONFIG_ALPHA_CIA) 215 # include <asm/core_cia.h> 216 #elif defined(CONFIG_ALPHA_IRONGATE) 217 # include <asm/core_irongate.h> 218 #elif defined(CONFIG_ALPHA_JENSEN) 219 # include <asm/jensen.h> 220 #elif defined(CONFIG_ALPHA_LCA) 221 # include <asm/core_lca.h> 222 #elif defined(CONFIG_ALPHA_MARVEL) 223 # include <asm/core_marvel.h> 224 #elif defined(CONFIG_ALPHA_MCPCIA) 225 # include <asm/core_mcpcia.h> 226 #elif defined(CONFIG_ALPHA_POLARIS) 227 # include <asm/core_polaris.h> 228 #elif defined(CONFIG_ALPHA_T2) 229 # include <asm/core_t2.h> 230 #elif defined(CONFIG_ALPHA_TSUNAMI) 231 # include <asm/core_tsunami.h> 232 #elif defined(CONFIG_ALPHA_TITAN) 233 # include <asm/core_titan.h> 234 #elif defined(CONFIG_ALPHA_WILDFIRE) 235 # include <asm/core_wildfire.h> 236 #else 237 #error "What system is this?" 238 #endif 239 240 #endif /* GENERIC */ 241 242 /* 243 * We always have external versions of these routines. 244 */ 245 extern u8 inb(unsigned long port); 246 extern u16 inw(unsigned long port); 247 extern u32 inl(unsigned long port); 248 extern void outb(u8 b, unsigned long port); 249 extern void outw(u16 b, unsigned long port); 250 extern void outl(u32 b, unsigned long port); 251 252 extern u8 readb(const volatile void __iomem *addr); 253 extern u16 readw(const volatile void __iomem *addr); 254 extern u32 readl(const volatile void __iomem *addr); 255 extern u64 readq(const volatile void __iomem *addr); 256 extern void writeb(u8 b, volatile void __iomem *addr); 257 extern void writew(u16 b, volatile void __iomem *addr); 258 extern void writel(u32 b, volatile void __iomem *addr); 259 extern void writeq(u64 b, volatile void __iomem *addr); 260 261 extern u8 __raw_readb(const volatile void __iomem *addr); 262 extern u16 __raw_readw(const volatile void __iomem *addr); 263 extern u32 __raw_readl(const volatile void __iomem *addr); 264 extern u64 __raw_readq(const volatile void __iomem *addr); 265 extern void __raw_writeb(u8 b, volatile void __iomem *addr); 266 extern void __raw_writew(u16 b, volatile void __iomem *addr); 267 extern void __raw_writel(u32 b, volatile void __iomem *addr); 268 extern void __raw_writeq(u64 b, volatile void __iomem *addr); 269 270 /* 271 * Mapping from port numbers to __iomem space is pretty easy. 272 */ 273 274 /* These two have to be extern inline because of the extern prototype from 275 <asm-generic/iomap.h>. It is not legal to mix "extern" and "static" for 276 the same declaration. */ 277 extern inline void __iomem *ioport_map(unsigned long port, unsigned int size) 278 { 279 return IO_CONCAT(__IO_PREFIX,ioportmap) (port); 280 } 281 282 extern inline void ioport_unmap(void __iomem *addr) 283 { 284 } 285 286 static inline void __iomem *ioremap(unsigned long port, unsigned long size) 287 { 288 return IO_CONCAT(__IO_PREFIX,ioremap) (port, size); 289 } 290 291 static inline void __iomem *__ioremap(unsigned long port, unsigned long size, 292 unsigned long flags) 293 { 294 return ioremap(port, size); 295 } 296 297 static inline void __iomem * ioremap_nocache(unsigned long offset, 298 unsigned long size) 299 { 300 return ioremap(offset, size); 301 } 302 303 #define ioremap_wc ioremap_nocache 304 #define ioremap_uc ioremap_nocache 305 306 static inline void iounmap(volatile void __iomem *addr) 307 { 308 IO_CONCAT(__IO_PREFIX,iounmap)(addr); 309 } 310 311 static inline int __is_ioaddr(unsigned long addr) 312 { 313 return IO_CONCAT(__IO_PREFIX,is_ioaddr)(addr); 314 } 315 #define __is_ioaddr(a) __is_ioaddr((unsigned long)(a)) 316 317 static inline int __is_mmio(const volatile void __iomem *addr) 318 { 319 return IO_CONCAT(__IO_PREFIX,is_mmio)(addr); 320 } 321 322 323 /* 324 * If the actual I/O bits are sufficiently trivial, then expand inline. 325 */ 326 327 #if IO_CONCAT(__IO_PREFIX,trivial_io_bw) 328 extern inline unsigned int ioread8(void __iomem *addr) 329 { 330 unsigned int ret = IO_CONCAT(__IO_PREFIX,ioread8)(addr); 331 mb(); 332 return ret; 333 } 334 335 extern inline unsigned int ioread16(void __iomem *addr) 336 { 337 unsigned int ret = IO_CONCAT(__IO_PREFIX,ioread16)(addr); 338 mb(); 339 return ret; 340 } 341 342 extern inline void iowrite8(u8 b, void __iomem *addr) 343 { 344 IO_CONCAT(__IO_PREFIX,iowrite8)(b, addr); 345 mb(); 346 } 347 348 extern inline void iowrite16(u16 b, void __iomem *addr) 349 { 350 IO_CONCAT(__IO_PREFIX,iowrite16)(b, addr); 351 mb(); 352 } 353 354 extern inline u8 inb(unsigned long port) 355 { 356 return ioread8(ioport_map(port, 1)); 357 } 358 359 extern inline u16 inw(unsigned long port) 360 { 361 return ioread16(ioport_map(port, 2)); 362 } 363 364 extern inline void outb(u8 b, unsigned long port) 365 { 366 iowrite8(b, ioport_map(port, 1)); 367 } 368 369 extern inline void outw(u16 b, unsigned long port) 370 { 371 iowrite16(b, ioport_map(port, 2)); 372 } 373 #endif 374 375 #if IO_CONCAT(__IO_PREFIX,trivial_io_lq) 376 extern inline unsigned int ioread32(void __iomem *addr) 377 { 378 unsigned int ret = IO_CONCAT(__IO_PREFIX,ioread32)(addr); 379 mb(); 380 return ret; 381 } 382 383 extern inline void iowrite32(u32 b, void __iomem *addr) 384 { 385 IO_CONCAT(__IO_PREFIX,iowrite32)(b, addr); 386 mb(); 387 } 388 389 extern inline u32 inl(unsigned long port) 390 { 391 return ioread32(ioport_map(port, 4)); 392 } 393 394 extern inline void outl(u32 b, unsigned long port) 395 { 396 iowrite32(b, ioport_map(port, 4)); 397 } 398 #endif 399 400 #if IO_CONCAT(__IO_PREFIX,trivial_rw_bw) == 1 401 extern inline u8 __raw_readb(const volatile void __iomem *addr) 402 { 403 return IO_CONCAT(__IO_PREFIX,readb)(addr); 404 } 405 406 extern inline u16 __raw_readw(const volatile void __iomem *addr) 407 { 408 return IO_CONCAT(__IO_PREFIX,readw)(addr); 409 } 410 411 extern inline void __raw_writeb(u8 b, volatile void __iomem *addr) 412 { 413 IO_CONCAT(__IO_PREFIX,writeb)(b, addr); 414 } 415 416 extern inline void __raw_writew(u16 b, volatile void __iomem *addr) 417 { 418 IO_CONCAT(__IO_PREFIX,writew)(b, addr); 419 } 420 421 extern inline u8 readb(const volatile void __iomem *addr) 422 { 423 u8 ret = __raw_readb(addr); 424 mb(); 425 return ret; 426 } 427 428 extern inline u16 readw(const volatile void __iomem *addr) 429 { 430 u16 ret = __raw_readw(addr); 431 mb(); 432 return ret; 433 } 434 435 extern inline void writeb(u8 b, volatile void __iomem *addr) 436 { 437 __raw_writeb(b, addr); 438 mb(); 439 } 440 441 extern inline void writew(u16 b, volatile void __iomem *addr) 442 { 443 __raw_writew(b, addr); 444 mb(); 445 } 446 #endif 447 448 #if IO_CONCAT(__IO_PREFIX,trivial_rw_lq) == 1 449 extern inline u32 __raw_readl(const volatile void __iomem *addr) 450 { 451 return IO_CONCAT(__IO_PREFIX,readl)(addr); 452 } 453 454 extern inline u64 __raw_readq(const volatile void __iomem *addr) 455 { 456 return IO_CONCAT(__IO_PREFIX,readq)(addr); 457 } 458 459 extern inline void __raw_writel(u32 b, volatile void __iomem *addr) 460 { 461 IO_CONCAT(__IO_PREFIX,writel)(b, addr); 462 } 463 464 extern inline void __raw_writeq(u64 b, volatile void __iomem *addr) 465 { 466 IO_CONCAT(__IO_PREFIX,writeq)(b, addr); 467 } 468 469 extern inline u32 readl(const volatile void __iomem *addr) 470 { 471 u32 ret = __raw_readl(addr); 472 mb(); 473 return ret; 474 } 475 476 extern inline u64 readq(const volatile void __iomem *addr) 477 { 478 u64 ret = __raw_readq(addr); 479 mb(); 480 return ret; 481 } 482 483 extern inline void writel(u32 b, volatile void __iomem *addr) 484 { 485 __raw_writel(b, addr); 486 mb(); 487 } 488 489 extern inline void writeq(u64 b, volatile void __iomem *addr) 490 { 491 __raw_writeq(b, addr); 492 mb(); 493 } 494 #endif 495 496 #define ioread16be(p) be16_to_cpu(ioread16(p)) 497 #define ioread32be(p) be32_to_cpu(ioread32(p)) 498 #define iowrite16be(v,p) iowrite16(cpu_to_be16(v), (p)) 499 #define iowrite32be(v,p) iowrite32(cpu_to_be32(v), (p)) 500 501 #define inb_p inb 502 #define inw_p inw 503 #define inl_p inl 504 #define outb_p outb 505 #define outw_p outw 506 #define outl_p outl 507 #define readb_relaxed(addr) __raw_readb(addr) 508 #define readw_relaxed(addr) __raw_readw(addr) 509 #define readl_relaxed(addr) __raw_readl(addr) 510 #define readq_relaxed(addr) __raw_readq(addr) 511 #define writeb_relaxed(b, addr) __raw_writeb(b, addr) 512 #define writew_relaxed(b, addr) __raw_writew(b, addr) 513 #define writel_relaxed(b, addr) __raw_writel(b, addr) 514 #define writeq_relaxed(b, addr) __raw_writeq(b, addr) 515 516 #define mmiowb() 517 518 /* 519 * String version of IO memory access ops: 520 */ 521 extern void memcpy_fromio(void *, const volatile void __iomem *, long); 522 extern void memcpy_toio(volatile void __iomem *, const void *, long); 523 extern void _memset_c_io(volatile void __iomem *, unsigned long, long); 524 525 static inline void memset_io(volatile void __iomem *addr, u8 c, long len) 526 { 527 _memset_c_io(addr, 0x0101010101010101UL * c, len); 528 } 529 530 #define __HAVE_ARCH_MEMSETW_IO 531 static inline void memsetw_io(volatile void __iomem *addr, u16 c, long len) 532 { 533 _memset_c_io(addr, 0x0001000100010001UL * c, len); 534 } 535 536 /* 537 * String versions of in/out ops: 538 */ 539 extern void insb (unsigned long port, void *dst, unsigned long count); 540 extern void insw (unsigned long port, void *dst, unsigned long count); 541 extern void insl (unsigned long port, void *dst, unsigned long count); 542 extern void outsb (unsigned long port, const void *src, unsigned long count); 543 extern void outsw (unsigned long port, const void *src, unsigned long count); 544 extern void outsl (unsigned long port, const void *src, unsigned long count); 545 546 /* 547 * The Alpha Jensen hardware for some rather strange reason puts 548 * the RTC clock at 0x170 instead of 0x70. Probably due to some 549 * misguided idea about using 0x70 for NMI stuff. 550 * 551 * These defines will override the defaults when doing RTC queries 552 */ 553 554 #ifdef CONFIG_ALPHA_GENERIC 555 # define RTC_PORT(x) ((x) + alpha_mv.rtc_port) 556 #else 557 # ifdef CONFIG_ALPHA_JENSEN 558 # define RTC_PORT(x) (0x170+(x)) 559 # else 560 # define RTC_PORT(x) (0x70 + (x)) 561 # endif 562 #endif 563 #define RTC_ALWAYS_BCD 0 564 565 /* 566 * Some mucking forons use if[n]def writeq to check if platform has it. 567 * It's a bloody bad idea and we probably want ARCH_HAS_WRITEQ for them 568 * to play with; for now just use cpp anti-recursion logics and make sure 569 * that damn thing is defined and expands to itself. 570 */ 571 572 #define writeq writeq 573 #define readq readq 574 575 /* 576 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 577 * access 578 */ 579 #define xlate_dev_mem_ptr(p) __va(p) 580 581 /* 582 * Convert a virtual cached pointer to an uncached pointer 583 */ 584 #define xlate_dev_kmem_ptr(p) p 585 586 #endif /* __KERNEL__ */ 587 588 #endif /* __ALPHA_IO_H */ 589