1 #ifndef __ASM_ALPHA_FPU_H 2 #define __ASM_ALPHA_FPU_H 3 4 #ifdef __KERNEL__ 5 #include <asm/special_insns.h> 6 #endif 7 8 /* 9 * Alpha floating-point control register defines: 10 */ 11 #define FPCR_DNOD (1UL<<47) /* denorm INV trap disable */ 12 #define FPCR_DNZ (1UL<<48) /* denorms to zero */ 13 #define FPCR_INVD (1UL<<49) /* invalid op disable (opt.) */ 14 #define FPCR_DZED (1UL<<50) /* division by zero disable (opt.) */ 15 #define FPCR_OVFD (1UL<<51) /* overflow disable (optional) */ 16 #define FPCR_INV (1UL<<52) /* invalid operation */ 17 #define FPCR_DZE (1UL<<53) /* division by zero */ 18 #define FPCR_OVF (1UL<<54) /* overflow */ 19 #define FPCR_UNF (1UL<<55) /* underflow */ 20 #define FPCR_INE (1UL<<56) /* inexact */ 21 #define FPCR_IOV (1UL<<57) /* integer overflow */ 22 #define FPCR_UNDZ (1UL<<60) /* underflow to zero (opt.) */ 23 #define FPCR_UNFD (1UL<<61) /* underflow disable (opt.) */ 24 #define FPCR_INED (1UL<<62) /* inexact disable (opt.) */ 25 #define FPCR_SUM (1UL<<63) /* summary bit */ 26 27 #define FPCR_DYN_SHIFT 58 /* first dynamic rounding mode bit */ 28 #define FPCR_DYN_CHOPPED (0x0UL << FPCR_DYN_SHIFT) /* towards 0 */ 29 #define FPCR_DYN_MINUS (0x1UL << FPCR_DYN_SHIFT) /* towards -INF */ 30 #define FPCR_DYN_NORMAL (0x2UL << FPCR_DYN_SHIFT) /* towards nearest */ 31 #define FPCR_DYN_PLUS (0x3UL << FPCR_DYN_SHIFT) /* towards +INF */ 32 #define FPCR_DYN_MASK (0x3UL << FPCR_DYN_SHIFT) 33 34 #define FPCR_MASK 0xffff800000000000L 35 36 /* 37 * IEEE trap enables are implemented in software. These per-thread 38 * bits are stored in the "ieee_state" field of "struct thread_info". 39 * Thus, the bits are defined so as not to conflict with the 40 * floating-point enable bit (which is architected). On top of that, 41 * we want to make these bits compatible with OSF/1 so 42 * ieee_set_fp_control() etc. can be implemented easily and 43 * compatibly. The corresponding definitions are in 44 * /usr/include/machine/fpu.h under OSF/1. 45 */ 46 #define IEEE_TRAP_ENABLE_INV (1UL<<1) /* invalid op */ 47 #define IEEE_TRAP_ENABLE_DZE (1UL<<2) /* division by zero */ 48 #define IEEE_TRAP_ENABLE_OVF (1UL<<3) /* overflow */ 49 #define IEEE_TRAP_ENABLE_UNF (1UL<<4) /* underflow */ 50 #define IEEE_TRAP_ENABLE_INE (1UL<<5) /* inexact */ 51 #define IEEE_TRAP_ENABLE_DNO (1UL<<6) /* denorm */ 52 #define IEEE_TRAP_ENABLE_MASK (IEEE_TRAP_ENABLE_INV | IEEE_TRAP_ENABLE_DZE |\ 53 IEEE_TRAP_ENABLE_OVF | IEEE_TRAP_ENABLE_UNF |\ 54 IEEE_TRAP_ENABLE_INE | IEEE_TRAP_ENABLE_DNO) 55 56 /* Denorm and Underflow flushing */ 57 #define IEEE_MAP_DMZ (1UL<<12) /* Map denorm inputs to zero */ 58 #define IEEE_MAP_UMZ (1UL<<13) /* Map underflowed outputs to zero */ 59 60 #define IEEE_MAP_MASK (IEEE_MAP_DMZ | IEEE_MAP_UMZ) 61 62 /* status bits coming from fpcr: */ 63 #define IEEE_STATUS_INV (1UL<<17) 64 #define IEEE_STATUS_DZE (1UL<<18) 65 #define IEEE_STATUS_OVF (1UL<<19) 66 #define IEEE_STATUS_UNF (1UL<<20) 67 #define IEEE_STATUS_INE (1UL<<21) 68 #define IEEE_STATUS_DNO (1UL<<22) 69 70 #define IEEE_STATUS_MASK (IEEE_STATUS_INV | IEEE_STATUS_DZE | \ 71 IEEE_STATUS_OVF | IEEE_STATUS_UNF | \ 72 IEEE_STATUS_INE | IEEE_STATUS_DNO) 73 74 #define IEEE_SW_MASK (IEEE_TRAP_ENABLE_MASK | \ 75 IEEE_STATUS_MASK | IEEE_MAP_MASK) 76 77 #define IEEE_CURRENT_RM_SHIFT 32 78 #define IEEE_CURRENT_RM_MASK (3UL<<IEEE_CURRENT_RM_SHIFT) 79 80 #define IEEE_STATUS_TO_EXCSUM_SHIFT 16 81 82 #define IEEE_INHERIT (1UL<<63) /* inherit on thread create? */ 83 84 /* 85 * Convert the software IEEE trap enable and status bits into the 86 * hardware fpcr format. 87 * 88 * Digital Unix engineers receive my thanks for not defining the 89 * software bits identical to the hardware bits. The chip designers 90 * receive my thanks for making all the not-implemented fpcr bits 91 * RAZ forcing us to use system calls to read/write this value. 92 */ 93 94 static inline unsigned long 95 ieee_swcr_to_fpcr(unsigned long sw) 96 { 97 unsigned long fp; 98 fp = (sw & IEEE_STATUS_MASK) << 35; 99 fp |= (sw & IEEE_MAP_DMZ) << 36; 100 fp |= (sw & IEEE_STATUS_MASK ? FPCR_SUM : 0); 101 fp |= (~sw & (IEEE_TRAP_ENABLE_INV 102 | IEEE_TRAP_ENABLE_DZE 103 | IEEE_TRAP_ENABLE_OVF)) << 48; 104 fp |= (~sw & (IEEE_TRAP_ENABLE_UNF | IEEE_TRAP_ENABLE_INE)) << 57; 105 fp |= (sw & IEEE_MAP_UMZ ? FPCR_UNDZ | FPCR_UNFD : 0); 106 fp |= (~sw & IEEE_TRAP_ENABLE_DNO) << 41; 107 return fp; 108 } 109 110 static inline unsigned long 111 ieee_fpcr_to_swcr(unsigned long fp) 112 { 113 unsigned long sw; 114 sw = (fp >> 35) & IEEE_STATUS_MASK; 115 sw |= (fp >> 36) & IEEE_MAP_DMZ; 116 sw |= (~fp >> 48) & (IEEE_TRAP_ENABLE_INV 117 | IEEE_TRAP_ENABLE_DZE 118 | IEEE_TRAP_ENABLE_OVF); 119 sw |= (~fp >> 57) & (IEEE_TRAP_ENABLE_UNF | IEEE_TRAP_ENABLE_INE); 120 sw |= (fp >> 47) & IEEE_MAP_UMZ; 121 sw |= (~fp >> 41) & IEEE_TRAP_ENABLE_DNO; 122 return sw; 123 } 124 125 #ifdef __KERNEL__ 126 127 /* The following two functions don't need trapb/excb instructions 128 around the mf_fpcr/mt_fpcr instructions because (a) the kernel 129 never generates arithmetic faults and (b) call_pal instructions 130 are implied trap barriers. */ 131 132 static inline unsigned long 133 rdfpcr(void) 134 { 135 unsigned long tmp, ret; 136 137 #if defined(CONFIG_ALPHA_EV6) || defined(CONFIG_ALPHA_EV67) 138 __asm__ __volatile__ ( 139 "ftoit $f0,%0\n\t" 140 "mf_fpcr $f0\n\t" 141 "ftoit $f0,%1\n\t" 142 "itoft %0,$f0" 143 : "=r"(tmp), "=r"(ret)); 144 #else 145 __asm__ __volatile__ ( 146 "stt $f0,%0\n\t" 147 "mf_fpcr $f0\n\t" 148 "stt $f0,%1\n\t" 149 "ldt $f0,%0" 150 : "=m"(tmp), "=m"(ret)); 151 #endif 152 153 return ret; 154 } 155 156 static inline void 157 wrfpcr(unsigned long val) 158 { 159 unsigned long tmp; 160 161 #if defined(CONFIG_ALPHA_EV6) || defined(CONFIG_ALPHA_EV67) 162 __asm__ __volatile__ ( 163 "ftoit $f0,%0\n\t" 164 "itoft %1,$f0\n\t" 165 "mt_fpcr $f0\n\t" 166 "itoft %0,$f0" 167 : "=&r"(tmp) : "r"(val)); 168 #else 169 __asm__ __volatile__ ( 170 "stt $f0,%0\n\t" 171 "ldt $f0,%1\n\t" 172 "mt_fpcr $f0\n\t" 173 "ldt $f0,%0" 174 : "=m"(tmp) : "m"(val)); 175 #endif 176 } 177 178 static inline unsigned long 179 swcr_update_status(unsigned long swcr, unsigned long fpcr) 180 { 181 /* EV6 implements most of the bits in hardware. Collect 182 the acrued exception bits from the real fpcr. */ 183 if (implver() == IMPLVER_EV6) { 184 swcr &= ~IEEE_STATUS_MASK; 185 swcr |= (fpcr >> 35) & IEEE_STATUS_MASK; 186 } 187 return swcr; 188 } 189 190 extern unsigned long alpha_read_fp_reg (unsigned long reg); 191 extern void alpha_write_fp_reg (unsigned long reg, unsigned long val); 192 extern unsigned long alpha_read_fp_reg_s (unsigned long reg); 193 extern void alpha_write_fp_reg_s (unsigned long reg, unsigned long val); 194 195 #endif /* __KERNEL__ */ 196 197 #endif /* __ASM_ALPHA_FPU_H */ 198