1.. SPDX-License-Identifier: GPL-2.0
2
3=================
4KVM Lock Overview
5=================
6
71. Acquisition Orders
8---------------------
9
10The acquisition orders for mutexes are as follows:
11
12- kvm->lock is taken outside vcpu->mutex
13
14- kvm->lock is taken outside kvm->slots_lock and kvm->irq_lock
15
16- kvm->slots_lock is taken outside kvm->irq_lock, though acquiring
17  them together is quite rare.
18
19On x86:
20
21- vcpu->mutex is taken outside kvm->arch.hyperv.hv_lock
22
23- kvm->arch.mmu_lock is an rwlock.  kvm->arch.tdp_mmu_pages_lock is
24  taken inside kvm->arch.mmu_lock, and cannot be taken without already
25  holding kvm->arch.mmu_lock (typically with ``read_lock``, otherwise
26  there's no need to take kvm->arch.tdp_mmu_pages_lock at all).
27
28Everything else is a leaf: no other lock is taken inside the critical
29sections.
30
312. Exception
32------------
33
34Fast page fault:
35
36Fast page fault is the fast path which fixes the guest page fault out of
37the mmu-lock on x86. Currently, the page fault can be fast in one of the
38following two cases:
39
401. Access Tracking: The SPTE is not present, but it is marked for access
41   tracking i.e. the SPTE_SPECIAL_MASK is set. That means we need to
42   restore the saved R/X bits. This is described in more detail later below.
43
442. Write-Protection: The SPTE is present and the fault is
45   caused by write-protect. That means we just need to change the W bit of
46   the spte.
47
48What we use to avoid all the race is the SPTE_HOST_WRITEABLE bit and
49SPTE_MMU_WRITEABLE bit on the spte:
50
51- SPTE_HOST_WRITEABLE means the gfn is writable on host.
52- SPTE_MMU_WRITEABLE means the gfn is writable on mmu. The bit is set when
53  the gfn is writable on guest mmu and it is not write-protected by shadow
54  page write-protection.
55
56On fast page fault path, we will use cmpxchg to atomically set the spte W
57bit if spte.SPTE_HOST_WRITEABLE = 1 and spte.SPTE_WRITE_PROTECT = 1, or
58restore the saved R/X bits if VMX_EPT_TRACK_ACCESS mask is set, or both. This
59is safe because whenever changing these bits can be detected by cmpxchg.
60
61But we need carefully check these cases:
62
631) The mapping from gfn to pfn
64
65The mapping from gfn to pfn may be changed since we can only ensure the pfn
66is not changed during cmpxchg. This is a ABA problem, for example, below case
67will happen:
68
69+------------------------------------------------------------------------+
70| At the beginning::                                                     |
71|                                                                        |
72|	gpte = gfn1                                                      |
73|	gfn1 is mapped to pfn1 on host                                   |
74|	spte is the shadow page table entry corresponding with gpte and  |
75|	spte = pfn1                                                      |
76+------------------------------------------------------------------------+
77| On fast page fault path:                                               |
78+------------------------------------+-----------------------------------+
79| CPU 0:                             | CPU 1:                            |
80+------------------------------------+-----------------------------------+
81| ::                                 |                                   |
82|                                    |                                   |
83|   old_spte = *spte;                |                                   |
84+------------------------------------+-----------------------------------+
85|                                    | pfn1 is swapped out::             |
86|                                    |                                   |
87|                                    |    spte = 0;                      |
88|                                    |                                   |
89|                                    | pfn1 is re-alloced for gfn2.      |
90|                                    |                                   |
91|                                    | gpte is changed to point to       |
92|                                    | gfn2 by the guest::               |
93|                                    |                                   |
94|                                    |    spte = pfn1;                   |
95+------------------------------------+-----------------------------------+
96| ::                                                                     |
97|                                                                        |
98|   if (cmpxchg(spte, old_spte, old_spte+W)                              |
99|	mark_page_dirty(vcpu->kvm, gfn1)                                 |
100|            OOPS!!!                                                     |
101+------------------------------------------------------------------------+
102
103We dirty-log for gfn1, that means gfn2 is lost in dirty-bitmap.
104
105For direct sp, we can easily avoid it since the spte of direct sp is fixed
106to gfn.  For indirect sp, we disabled fast page fault for simplicity.
107
108A solution for indirect sp could be to pin the gfn, for example via
109kvm_vcpu_gfn_to_pfn_atomic, before the cmpxchg.  After the pinning:
110
111- We have held the refcount of pfn that means the pfn can not be freed and
112  be reused for another gfn.
113- The pfn is writable and therefore it cannot be shared between different gfns
114  by KSM.
115
116Then, we can ensure the dirty bitmaps is correctly set for a gfn.
117
1182) Dirty bit tracking
119
120In the origin code, the spte can be fast updated (non-atomically) if the
121spte is read-only and the Accessed bit has already been set since the
122Accessed bit and Dirty bit can not be lost.
123
124But it is not true after fast page fault since the spte can be marked
125writable between reading spte and updating spte. Like below case:
126
127+------------------------------------------------------------------------+
128| At the beginning::                                                     |
129|                                                                        |
130|	spte.W = 0                                                       |
131|	spte.Accessed = 1                                                |
132+------------------------------------+-----------------------------------+
133| CPU 0:                             | CPU 1:                            |
134+------------------------------------+-----------------------------------+
135| In mmu_spte_clear_track_bits()::   |                                   |
136|                                    |                                   |
137|  old_spte = *spte;                 |                                   |
138|                                    |                                   |
139|                                    |                                   |
140|  /* 'if' condition is satisfied. */|                                   |
141|  if (old_spte.Accessed == 1 &&     |                                   |
142|       old_spte.W == 0)             |                                   |
143|     spte = 0ull;                   |                                   |
144+------------------------------------+-----------------------------------+
145|                                    | on fast page fault path::         |
146|                                    |                                   |
147|                                    |    spte.W = 1                     |
148|                                    |                                   |
149|                                    | memory write on the spte::        |
150|                                    |                                   |
151|                                    |    spte.Dirty = 1                 |
152+------------------------------------+-----------------------------------+
153|  ::                                |                                   |
154|                                    |                                   |
155|   else                             |                                   |
156|     old_spte = xchg(spte, 0ull)    |                                   |
157|   if (old_spte.Accessed == 1)      |                                   |
158|     kvm_set_pfn_accessed(spte.pfn);|                                   |
159|   if (old_spte.Dirty == 1)         |                                   |
160|     kvm_set_pfn_dirty(spte.pfn);   |                                   |
161|     OOPS!!!                        |                                   |
162+------------------------------------+-----------------------------------+
163
164The Dirty bit is lost in this case.
165
166In order to avoid this kind of issue, we always treat the spte as "volatile"
167if it can be updated out of mmu-lock, see spte_has_volatile_bits(), it means,
168the spte is always atomically updated in this case.
169
1703) flush tlbs due to spte updated
171
172If the spte is updated from writable to readonly, we should flush all TLBs,
173otherwise rmap_write_protect will find a read-only spte, even though the
174writable spte might be cached on a CPU's TLB.
175
176As mentioned before, the spte can be updated to writable out of mmu-lock on
177fast page fault path, in order to easily audit the path, we see if TLBs need
178be flushed caused by this reason in mmu_spte_update() since this is a common
179function to update spte (present -> present).
180
181Since the spte is "volatile" if it can be updated out of mmu-lock, we always
182atomically update the spte, the race caused by fast page fault can be avoided,
183See the comments in spte_has_volatile_bits() and mmu_spte_update().
184
185Lockless Access Tracking:
186
187This is used for Intel CPUs that are using EPT but do not support the EPT A/D
188bits. In this case, when the KVM MMU notifier is called to track accesses to a
189page (via kvm_mmu_notifier_clear_flush_young), it marks the PTE as not-present
190by clearing the RWX bits in the PTE and storing the original R & X bits in
191some unused/ignored bits. In addition, the SPTE_SPECIAL_MASK is also set on the
192PTE (using the ignored bit 62). When the VM tries to access the page later on,
193a fault is generated and the fast page fault mechanism described above is used
194to atomically restore the PTE to a Present state. The W bit is not saved when
195the PTE is marked for access tracking and during restoration to the Present
196state, the W bit is set depending on whether or not it was a write access. If
197it wasn't, then the W bit will remain clear until a write access happens, at
198which time it will be set using the Dirty tracking mechanism described above.
199
2003. Reference
201------------
202
203:Name:		kvm_lock
204:Type:		mutex
205:Arch:		any
206:Protects:	- vm_list
207
208:Name:		kvm_count_lock
209:Type:		raw_spinlock_t
210:Arch:		any
211:Protects:	- hardware virtualization enable/disable
212:Comment:	'raw' because hardware enabling/disabling must be atomic /wrt
213		migration.
214
215:Name:		kvm_arch::tsc_write_lock
216:Type:		raw_spinlock
217:Arch:		x86
218:Protects:	- kvm_arch::{last_tsc_write,last_tsc_nsec,last_tsc_offset}
219		- tsc offset in vmcb
220:Comment:	'raw' because updating the tsc offsets must not be preempted.
221
222:Name:		kvm->mmu_lock
223:Type:		spinlock_t
224:Arch:		any
225:Protects:	-shadow page/shadow tlb entry
226:Comment:	it is a spinlock since it is used in mmu notifier.
227
228:Name:		kvm->srcu
229:Type:		srcu lock
230:Arch:		any
231:Protects:	- kvm->memslots
232		- kvm->buses
233:Comment:	The srcu read lock must be held while accessing memslots (e.g.
234		when using gfn_to_* functions) and while accessing in-kernel
235		MMIO/PIO address->device structure mapping (kvm->buses).
236		The srcu index can be stored in kvm_vcpu->srcu_idx per vcpu
237		if it is needed by multiple functions.
238
239:Name:		blocked_vcpu_on_cpu_lock
240:Type:		spinlock_t
241:Arch:		x86
242:Protects:	blocked_vcpu_on_cpu
243:Comment:	This is a per-CPU lock and it is used for VT-d posted-interrupts.
244		When VT-d posted-interrupts is supported and the VM has assigned
245		devices, we put the blocked vCPU on the list blocked_vcpu_on_cpu
246		protected by blocked_vcpu_on_cpu_lock, when VT-d hardware issues
247		wakeup notification event since external interrupts from the
248		assigned devices happens, we will find the vCPU on the list to
249		wakeup.
250