1.. SPDX-License-Identifier: GPL-2.0 2 3================= 4KVM Lock Overview 5================= 6 71. Acquisition Orders 8--------------------- 9 10The acquisition orders for mutexes are as follows: 11 12- cpus_read_lock() is taken outside kvm_lock and kvm_usage_lock 13 14- kvm->lock is taken outside vcpu->mutex 15 16- kvm->lock is taken outside kvm->slots_lock and kvm->irq_lock 17 18- kvm->slots_lock is taken outside kvm->irq_lock, though acquiring 19 them together is quite rare. 20 21- kvm->mn_active_invalidate_count ensures that pairs of 22 invalidate_range_start() and invalidate_range_end() callbacks 23 use the same memslots array. kvm->slots_lock and kvm->slots_arch_lock 24 are taken on the waiting side when modifying memslots, so MMU notifiers 25 must not take either kvm->slots_lock or kvm->slots_arch_lock. 26 27cpus_read_lock() vs kvm_lock: 28- Taking cpus_read_lock() outside of kvm_lock is problematic, despite that 29 being the official ordering, as it is quite easy to unknowingly trigger 30 cpus_read_lock() while holding kvm_lock. Use caution when walking vm_list, 31 e.g. avoid complex operations when possible. 32 33For SRCU: 34 35- ``synchronize_srcu(&kvm->srcu)`` is called inside critical sections 36 for kvm->lock, vcpu->mutex and kvm->slots_lock. These locks _cannot_ 37 be taken inside a kvm->srcu read-side critical section; that is, the 38 following is broken:: 39 40 srcu_read_lock(&kvm->srcu); 41 mutex_lock(&kvm->slots_lock); 42 43- kvm->slots_arch_lock instead is released before the call to 44 ``synchronize_srcu()``. It _can_ therefore be taken inside a 45 kvm->srcu read-side critical section, for example while processing 46 a vmexit. 47 48On x86: 49 50- vcpu->mutex is taken outside kvm->arch.hyperv.hv_lock and kvm->arch.xen.xen_lock 51 52- kvm->arch.mmu_lock is an rwlock. kvm->arch.tdp_mmu_pages_lock and 53 kvm->arch.mmu_unsync_pages_lock are taken inside kvm->arch.mmu_lock, and 54 cannot be taken without already holding kvm->arch.mmu_lock (typically with 55 ``read_lock`` for the TDP MMU, thus the need for additional spinlocks). 56 57Everything else is a leaf: no other lock is taken inside the critical 58sections. 59 602. Exception 61------------ 62 63Fast page fault: 64 65Fast page fault is the fast path which fixes the guest page fault out of 66the mmu-lock on x86. Currently, the page fault can be fast in one of the 67following two cases: 68 691. Access Tracking: The SPTE is not present, but it is marked for access 70 tracking. That means we need to restore the saved R/X bits. This is 71 described in more detail later below. 72 732. Write-Protection: The SPTE is present and the fault is caused by 74 write-protect. That means we just need to change the W bit of the spte. 75 76What we use to avoid all the races is the Host-writable bit and MMU-writable bit 77on the spte: 78 79- Host-writable means the gfn is writable in the host kernel page tables and in 80 its KVM memslot. 81- MMU-writable means the gfn is writable in the guest's mmu and it is not 82 write-protected by shadow page write-protection. 83 84On fast page fault path, we will use cmpxchg to atomically set the spte W 85bit if spte.HOST_WRITEABLE = 1 and spte.WRITE_PROTECT = 1, to restore the saved 86R/X bits if for an access-traced spte, or both. This is safe because whenever 87changing these bits can be detected by cmpxchg. 88 89But we need carefully check these cases: 90 911) The mapping from gfn to pfn 92 93The mapping from gfn to pfn may be changed since we can only ensure the pfn 94is not changed during cmpxchg. This is a ABA problem, for example, below case 95will happen: 96 97+------------------------------------------------------------------------+ 98| At the beginning:: | 99| | 100| gpte = gfn1 | 101| gfn1 is mapped to pfn1 on host | 102| spte is the shadow page table entry corresponding with gpte and | 103| spte = pfn1 | 104+------------------------------------------------------------------------+ 105| On fast page fault path: | 106+------------------------------------+-----------------------------------+ 107| CPU 0: | CPU 1: | 108+------------------------------------+-----------------------------------+ 109| :: | | 110| | | 111| old_spte = *spte; | | 112+------------------------------------+-----------------------------------+ 113| | pfn1 is swapped out:: | 114| | | 115| | spte = 0; | 116| | | 117| | pfn1 is re-alloced for gfn2. | 118| | | 119| | gpte is changed to point to | 120| | gfn2 by the guest:: | 121| | | 122| | spte = pfn1; | 123+------------------------------------+-----------------------------------+ 124| :: | 125| | 126| if (cmpxchg(spte, old_spte, old_spte+W) | 127| mark_page_dirty(vcpu->kvm, gfn1) | 128| OOPS!!! | 129+------------------------------------------------------------------------+ 130 131We dirty-log for gfn1, that means gfn2 is lost in dirty-bitmap. 132 133For direct sp, we can easily avoid it since the spte of direct sp is fixed 134to gfn. For indirect sp, we disabled fast page fault for simplicity. 135 136A solution for indirect sp could be to pin the gfn, for example via 137kvm_vcpu_gfn_to_pfn_atomic, before the cmpxchg. After the pinning: 138 139- We have held the refcount of pfn; that means the pfn can not be freed and 140 be reused for another gfn. 141- The pfn is writable and therefore it cannot be shared between different gfns 142 by KSM. 143 144Then, we can ensure the dirty bitmaps is correctly set for a gfn. 145 1462) Dirty bit tracking 147 148In the origin code, the spte can be fast updated (non-atomically) if the 149spte is read-only and the Accessed bit has already been set since the 150Accessed bit and Dirty bit can not be lost. 151 152But it is not true after fast page fault since the spte can be marked 153writable between reading spte and updating spte. Like below case: 154 155+------------------------------------------------------------------------+ 156| At the beginning:: | 157| | 158| spte.W = 0 | 159| spte.Accessed = 1 | 160+------------------------------------+-----------------------------------+ 161| CPU 0: | CPU 1: | 162+------------------------------------+-----------------------------------+ 163| In mmu_spte_clear_track_bits():: | | 164| | | 165| old_spte = *spte; | | 166| | | 167| | | 168| /* 'if' condition is satisfied. */| | 169| if (old_spte.Accessed == 1 && | | 170| old_spte.W == 0) | | 171| spte = 0ull; | | 172+------------------------------------+-----------------------------------+ 173| | on fast page fault path:: | 174| | | 175| | spte.W = 1 | 176| | | 177| | memory write on the spte:: | 178| | | 179| | spte.Dirty = 1 | 180+------------------------------------+-----------------------------------+ 181| :: | | 182| | | 183| else | | 184| old_spte = xchg(spte, 0ull) | | 185| if (old_spte.Accessed == 1) | | 186| kvm_set_pfn_accessed(spte.pfn);| | 187| if (old_spte.Dirty == 1) | | 188| kvm_set_pfn_dirty(spte.pfn); | | 189| OOPS!!! | | 190+------------------------------------+-----------------------------------+ 191 192The Dirty bit is lost in this case. 193 194In order to avoid this kind of issue, we always treat the spte as "volatile" 195if it can be updated out of mmu-lock [see spte_has_volatile_bits()]; it means 196the spte is always atomically updated in this case. 197 1983) flush tlbs due to spte updated 199 200If the spte is updated from writable to read-only, we should flush all TLBs, 201otherwise rmap_write_protect will find a read-only spte, even though the 202writable spte might be cached on a CPU's TLB. 203 204As mentioned before, the spte can be updated to writable out of mmu-lock on 205fast page fault path. In order to easily audit the path, we see if TLBs needing 206to be flushed caused this reason in mmu_spte_update() since this is a common 207function to update spte (present -> present). 208 209Since the spte is "volatile" if it can be updated out of mmu-lock, we always 210atomically update the spte and the race caused by fast page fault can be avoided. 211See the comments in spte_has_volatile_bits() and mmu_spte_update(). 212 213Lockless Access Tracking: 214 215This is used for Intel CPUs that are using EPT but do not support the EPT A/D 216bits. In this case, PTEs are tagged as A/D disabled (using ignored bits), and 217when the KVM MMU notifier is called to track accesses to a page (via 218kvm_mmu_notifier_clear_flush_young), it marks the PTE not-present in hardware 219by clearing the RWX bits in the PTE and storing the original R & X bits in more 220unused/ignored bits. When the VM tries to access the page later on, a fault is 221generated and the fast page fault mechanism described above is used to 222atomically restore the PTE to a Present state. The W bit is not saved when the 223PTE is marked for access tracking and during restoration to the Present state, 224the W bit is set depending on whether or not it was a write access. If it 225wasn't, then the W bit will remain clear until a write access happens, at which 226time it will be set using the Dirty tracking mechanism described above. 227 2283. Reference 229------------ 230 231``kvm_lock`` 232^^^^^^^^^^^^ 233 234:Type: mutex 235:Arch: any 236:Protects: - vm_list 237 238``kvm_usage_lock`` 239^^^^^^^^^^^^^^^^^^ 240 241:Type: mutex 242:Arch: any 243:Protects: - kvm_usage_count 244 - hardware virtualization enable/disable 245:Comment: Exists because using kvm_lock leads to deadlock (see earlier comment 246 on cpus_read_lock() vs kvm_lock). Note, KVM also disables CPU hotplug via 247 cpus_read_lock() when enabling/disabling virtualization. 248 249``kvm->mn_invalidate_lock`` 250^^^^^^^^^^^^^^^^^^^^^^^^^^^ 251 252:Type: spinlock_t 253:Arch: any 254:Protects: mn_active_invalidate_count, mn_memslots_update_rcuwait 255 256``kvm_arch::tsc_write_lock`` 257^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 258 259:Type: raw_spinlock_t 260:Arch: x86 261:Protects: - kvm_arch::{last_tsc_write,last_tsc_nsec,last_tsc_offset} 262 - tsc offset in vmcb 263:Comment: 'raw' because updating the tsc offsets must not be preempted. 264 265``kvm->mmu_lock`` 266^^^^^^^^^^^^^^^^^ 267:Type: spinlock_t or rwlock_t 268:Arch: any 269:Protects: -shadow page/shadow tlb entry 270:Comment: it is a spinlock since it is used in mmu notifier. 271 272``kvm->srcu`` 273^^^^^^^^^^^^^ 274:Type: srcu lock 275:Arch: any 276:Protects: - kvm->memslots 277 - kvm->buses 278:Comment: The srcu read lock must be held while accessing memslots (e.g. 279 when using gfn_to_* functions) and while accessing in-kernel 280 MMIO/PIO address->device structure mapping (kvm->buses). 281 The srcu index can be stored in kvm_vcpu->srcu_idx per vcpu 282 if it is needed by multiple functions. 283 284``kvm->slots_arch_lock`` 285^^^^^^^^^^^^^^^^^^^^^^^^ 286:Type: mutex 287:Arch: any (only needed on x86 though) 288:Protects: any arch-specific fields of memslots that have to be modified 289 in a ``kvm->srcu`` read-side critical section. 290:Comment: must be held before reading the pointer to the current memslots, 291 until after all changes to the memslots are complete 292 293``wakeup_vcpus_on_cpu_lock`` 294^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 295:Type: spinlock_t 296:Arch: x86 297:Protects: wakeup_vcpus_on_cpu 298:Comment: This is a per-CPU lock and it is used for VT-d posted-interrupts. 299 When VT-d posted-interrupts are supported and the VM has assigned 300 devices, we put the blocked vCPU on the list blocked_vcpu_on_cpu 301 protected by blocked_vcpu_on_cpu_lock. When VT-d hardware issues 302 wakeup notification event since external interrupts from the 303 assigned devices happens, we will find the vCPU on the list to 304 wakeup. 305 306``vendor_module_lock`` 307^^^^^^^^^^^^^^^^^^^^^^ 308:Type: mutex 309:Arch: x86 310:Protects: loading a vendor module (kvm_amd or kvm_intel) 311:Comment: Exists because using kvm_lock leads to deadlock. kvm_lock is taken 312 in notifiers, e.g. __kvmclock_cpufreq_notifier(), that may be invoked while 313 cpu_hotplug_lock is held, e.g. from cpufreq_boost_trigger_state(), and many 314 operations need to take cpu_hotplug_lock when loading a vendor module, e.g. 315 updating static calls. 316